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PDF CXD3021R Data sheet ( Hoja de datos )
| Número de pieza | CXD3021R | |
| Descripción | CD Digital Signal Processor with Built-in Digital Servo and DAC | |
| Fabricantes | Sony Corporation | |
| Logotipo |  |
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CXD3021R
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD3021R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
120 pin LQFP (Plastic)
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 32× continuous playback possible with a
low external clock
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 32× playback by switching the
built-in VCO
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL.
• Digital PLL master clock can be set to 2/3 the
conventional one.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 32× playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub-Q data error
detection
• Digital CLV spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high
accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• Digital Out can be generated from the audio serial
inputs.
• Supports three types of DA interface
(48 bits/64 bits/32 bits)
• DSP, servo and DAC blocks support sleep mode.
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump and surf brake functions supporting micro
two-axis
• Tracking filter: 6 stages
Focus filter: 5 stages
• Servo drive DAC output possible
Digital Filter and DAC Blocks
• Digital de-emphasis
• Digital attenuation
• 8fs oversampling filter
• Adoption of a tertiary ∆∑ noise shaper
• Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage
VDD –0.3 to +4.4 V
• Input voltage
VI –0.3 to +4.4 V
(VSS – 0.3 to VDD + 0.3) V
• Output voltage
VO –0.3 to +4.4 V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference VSS – AVSS –0.3 to +0.3 V
VDD – AVDD –0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage
VDD∗
3.0 to 4.0 V
• Operating temperature Topr
–20 to +75 °C
∗ The VDD (min.) for the CXD3021R varies according
to the playback speed and built-in VCO selection.
The VDD (min.) for the CXD3021R under various
conditions are as shown on the following page.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98209A9Z-PS
1 page  
CXD3021R
Pin Description
Pin
No.
Symbol
I/O
Description
1 SE
I
Sled error signal input.
2 FE
I
Focus error signal input.
3 VC
I
Center voltage input.
4 VPCO1 O 1, Z, 0 Wide-band EFM PLL VCO2 charge pump output.
5
VPCO2
O
1, Z, 0
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $EX
command FCSW.
6 VCTL
I
Wide-band EFM PLL VCO2 control voltage input.
7 FILO
O Analog Master PLL filter output (slave = digital PLL).
8 FILI
I
Master PLL filter input.
9 PCO
O 1, Z, 0 Master PLL charge pump output.
10 CLTV
I
Multiplier VCO control voltage input.
11 AVSS1
Analog GND.
12 RFAC I
EFM signal input.
13 BIAS
I
Asymmetry circuit constant current input.
14 ASYI
I
Asymmetry comparator voltage input.
15 ASYO O 1, 0 EFM full-swing output (low = VSS, high = VDD).
16 AVDD1
Analog power supply.
17 DVDD1
Digital power supply.
18 DVSS1
Digital GND.
19 ASYE I
Asymmetry circuit on/off (low = off, high = on).
20 PSSL
I
Audio data output mode switching input (low: serial, high: parallel).
21 WDCK O 1, 0 D/A interface for 48-bit slot. Word clock f = 2Fs.
22 LRCK O 1, 0 D/A interface for 48-bit slot. LR clock f = Fs.
23 LRCKI I
LR clock input to DAC (48-bit slot).
24 DA16
O
1, 0
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
25 PCMDI I
Audio data input to DAC (48-bit slot).
26 DA15 O 1, 0 DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
27 BCKI
I
Bit clock input to DAC (48-bit slot).
28 DA14
O
1, 0
DA14 output when PSSL = 1, 32-bit/64-bit slot serial data output (two'
complement, LSB first) when PSSL = 0.
29 DA13 O 1, 0 DA13 output when PSSL = 1, 32-bit/64-bit slot bit clock output when PSSL = 0.
30 DA12 O 1, 0 DA12 output when PSSL = 1, 32-bit/64-bit slot LR clock output when PSSL = 0.
31 DA11 O 1, 0 DA11 output when PSSL = 1, GTOP output when PSSL = 0.
32 DA10 O 1, 0 DA10 output when PSSL = 1, XUGF output when PSSL = 0.
33 DA09 O 1, 0 DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
–5–
5 Page 
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit
Clock frequency
fCK
16 MHz
Clock pulse width
tWCK
30
ns
Setup time
tSU 30
ns
Hold time
tH 30
ns
Delay time
tD 30
ns
Latch pulse width
tWL
750
ns
EXCK SQCK frequency fT
0.65 MHz
EXCK SQCK pulse width tWT
750
CNIN frequency ∗
fT
CNIN pulse width ∗
tWT
7.5
∗ Only when $44 and $45 are executed.
ns
65 kHz
µs
CLOK
1/fCK
tWCK
tWCK
DATA
XLAT
EXCK
SQCK
CNIN
SBSO
SQSO
tSU tH
tWT tWT
1/fT
tSU tH
tD tWL
CXD3021R
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CXD3021R.PDF ] | |
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