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PDF CXL5508P Data sheet ( Hoja de datos )

Número de pieza CXL5508P
Descripción CMOS-CCD 1H Delay Line for PAL
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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No Preview Available ! CXL5508P Hoja de datos, Descripción, Manual

CXL5508M/P
CMOS-CCD 1H Delay Line for PAL
Description
The CXL5508M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals, including
the external low-pass filter.
Features
Single 5V power supply
Low power consumption 60mW (Typ.)
Built-in peripheral circuits
Functions
565-bit CCD register
Clock driver
Auto-bias circuit
Input clamp circuit
Sample-and-hold circuit
Structure
CMOS-CCD
Blook Diagram and Pin Configuration (Top View)
CXL5508M
8 pin SOP (Plastic)
CXL5508P
8 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage
VDD
6
Operating temperature Topr –10 to +60
Storage temperature Tstg –55 to +150
Allowable power dissipation
PD
CXL5508M 350
CXL5508P 480
V
°C
°C
mW
mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage
VDD
5 ± 5% V
Recommended Clock Conditions (Ta = 25°C)
Input clock amplitude VCLK 0.3 to 1.0 Vp-p
(0.5Vp-p typ.)
Clock frequency
fCLK 8.867238 MHz
Input clock waveform Sine wave
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 527mVp-p (Max.)
(at internal clamp condition)
876 5
Auto-bias circuit
Bias circuit
CCD
(565bit)
Clamp circuit
1
Output circuit
(S/H 1bit)
23
Timing circuit
Clock driver
Bias circuit (A)
Bias circuit (B)
4
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E91101A7X-PS

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CXL5508P pdf
CXL5508M/P
–5–

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