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PDF CXL5513M Data sheet ( Hoja de datos )

Número de pieza CXL5513M
Descripción CMOS-CCD 1H Delay Line for NTSC
Fabricantes Sony Corporation 
Logotipo Sony Corporation Logotipo



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No Preview Available ! CXL5513M Hoja de datos, Descripción, Manual

CXL5513M/P
CMOS-CCD 1H Delay Line for NTSC
Description
The CXL5513M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1 H delay time for NTSC chroma signals
including the external lowpass filter.
CXL5513M
8 pin SOP (Plastic)
CXL5513P
8 pin DIP (Plastic)
Features
Single 5 V power supply
Low power consumption
Built-in peripheral circuit
Built-in tripling PLL circuit
Center bias mode
Absolute Maximum Ratings (Ta=25 °C)
Supply voltage VDD +6 V
Operating temperature Topr –10 to +60 °C
Storage temperature Tstg –55 to +150 °C
Allowable power dissipation
PD
CXL5513M 350 mW
CXL5513P 480 mW
Recommended Operating Range (Ta=25 ˚C)
VDD 5 V±5 %
Input Signal Amplitude
VSIG 500 mVp-p (typ.), 572 mVP-P (max.)
Functions
680-bit CCD register
Clock driver
Auto bias circuit
Input center bias circuit.
Sample and hold circuit
Tripling PLL circuit
Inverted output
Structure
CMOS-CCD
Recommended Clock Conditions (Ta=25 ˚C)
Input clock amplitude VCLK 400 mVp-p (Typ.)
Clock frequency
fCLK 3.579545 MHz
• Input clock waveform Sine wave
Block Diagram and Pin Configuration (Top View)
VDD VCO OUT
87
VCO IN
6
CLK
5
Auto-bias circuit
Bias circuit
CCD
(680bit)
Output circuit
(S/H 1 bit)
12
3
IN AB OUT
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
4
VSS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E93Y20-TE

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CXL5513M pdf
CXL5513M/P
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