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PDF 100329 Data sheet ( Hoja de datos )

Número de pieza 100329
Descripción Low Power Octal ECL/TTL Bidirectional Translator with Register
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! 100329 Hoja de datos, Descripción, Manual

September 1999
100329
Low Power Octal ECL/TTL Bidirectional Translator with
Register
General Description
The 100329 is an octal registered bidirectional translator de-
signed to convert TTL logic levels to 100K ECL logic levels
and vice versa. The direction of the translation is determined
by the DIR input. A LOW on the output enable input (OE)
holds the ECL outputs in a cut-off state and the TTL outputs
at a high impedance level. The outputs change synchro-
nously with the rising edge of the clock input (CP) even
though only one output is enabled at the time.
The cut-off state is designed to be more negative than a nor-
mal ECL LOW level. This allows the output emitter-followers
to turn off when the termination supply is −2.0V, presenting a
high impedance to the data bus. This high impedance re-
duces the termination power and prevents loss of low state
noise margin when several loads share the bus.
The 100329 is designed with FAST® TTL output buffers, fea-
turing optimal DC drive and capable of quickly charging and
discharging highly capacitive loads. All inputs have 50 k
pull-down resistors.
Features
n Bidirectional translation
n ECL high impedance outputs
n Registered outputs
n FAST TTL outputs
n TRI-STATE® outputs
n Voltage compensated operating range = −4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9206601
Connection Diagrams
24-Pin DIP
24-Pin Quad Cerpack
DS100306-2
DS100306-4
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FAST® is a registered trademark of Fairchild Semiconductor.
© 1999 National Semiconductor Corporation DS100306
www.national.com

1 page




100329 pdf
Military Version
ECL-to-TTL DC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −55˚C to +125˚C, CL = 50 pF, VTTL = +4.5V to + 5.5V
Symbol
Parameter
VOH Output HIGH Voltage
Min Max Units
TC
Conditions
2.5 mV 0˚C to +125˚C IOH = −1 mA, VTTL = 4.50V
2.4 −55˚C
VOL Output LOW Voltage
0.5 mV
−55˚C
+125˚C
IOL = 24 mA, VTTL = 4.50V
VIH Input HIGH Voltage −1165 −870 mV
−55˚C
Guaranteed HIGH Signal
+125˚C
for All Inputs
VIL
Input LOW Voltage
−1830 −1475 mV
−55˚C to
Guaranteed LOW Signal
+125˚C
for All Inputs
IIH
IIL
IOZHT
Input HIGH Current
Input LOW Current
TRI-STATE Current
Output High
350 µA
500
0.50 µA
70 µA
0˚C to
+125˚C
−55˚C to
+125˚C
−55˚C to
+125˚C
VEE = −5.7V
VIN = VIH (Max)
VEE = −4.2V
VIN = VIL (Min)
VOUT = +2.7V
IOZLT
TRI-STATE Current
Output Low
−1.0
mA
−55˚C to
VOUT = +0.5V
+125˚C
IOS
Output Short-Circuit
−60 −150 mA
−55˚C to
VOUT = 0.0V, VTTL = +5.5V
CURRENT
+125˚C
ITTL VTTL Supply Current
70 mA
47 mA
−55˚C to
+125˚C
TTL Outputs Low
TTL Output High
70 mA
TTL Output in TRI-STATE
Notes
(Notes 7, 8, 9)
(Notes 7, 8, 9, 10)
(Notes 7, 8, 9, 10)
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 9)
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals −55˚C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides “cold start” specs which can be considered a worst case
condition at cold temperatures.
Note 8: Screen tested 100% on each device at −55˚C, +25˚C, and +125˚C, Subgroups, 1, 2 3, 7, and 8.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at −55˚C, +25˚C, and +125˚C, Subgroups A1, 2, 3, 7, and 8.
Note 10: Guaranteed by applying specified input condition and testing VOH/VOL.
Military Version
TTL-to-ECL AC Electrical Characteristics
VEE = −4.2V to −5.7V, VTTL = +4.5V to +5.5V, VCC = VCCA = GND
Symbol
Parameter
TC = −55˚C TC = 25˚C
tPLH
tPHL
tPZH
tPHZ
tPHZ
tset
thold
tpw(H)
tTLH
tTHL
fMAX
CP to En
OE to En
(Cutoff to HIGH)
OE to En
(HIGH to Cutoff)
DIR to En
(HIGH to Cutoff)
Tn to CP
Tn to CP
Pulse Width CP
Transition Time
20% to 80%, 80% to 20%
CP
Min Max Min Max
1.3 3.8 1.6 3.7
1.0 4.3 1.5 4.4
1.5 5.0 1.6 4.5
1.6 4.7 1.6 4.3
2.5 2.0
2.5 2.0
2.5 2.0
0.4 2.3 0.5 2.1
250 250
TC =
+125˚C
Min Max
1.9 4.3
1.7 9.0
Units
ns
ns
ns
Conditions
Figures 1, 2
Figures 1, 2
1.6 5.0 ns Figures 1, 2
1.7 4.7 ns Figures 1, 2
2.5
2.5
2.5
0.4 2.4
ns Figures 1, 2
ns Figures 1, 2
ns Figures 1, 2
ns Figures 1, 2
250 MHz
Notes
(Notes 11,
12, 13)
(Notes 11,
12, 13)
(Note 14)
(Note 14)
(Note 14)
5 www.national.com

5 Page





100329 arduino
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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