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37LV36-P 데이터시트 PDF




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부품번호 37LV36-P 기능
기능 36K/ 64K/ and 128K Serial EPROM Family
제조업체 Microchip Technology
로고 Microchip Technology 로고


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37LV36-P 데이터시트, 핀배열, 회로
37LV36/65/128
36K, 64K, and 128K Serial EPROM Family
FEATURES
• Operationally equivalent to Xilinx® XC1700 family
• Wide voltage range 3.0 V to 6.0 V
• Maximum read current 10 mA at 5.0 V
• Standby current 100 µA typical
• Industry standard Synchronous Serial Interface/
1 bit per rising edge of clock
• Full Static Operation
• Sequential Read/Program
• Cascadable Output Enable
• 10 MHz Maximum Clock Rate @ 5.0 Vdc
• Programmable Polarity on Hardware Reset
• Programming with industry standard EPROM pro-
grammers
• Electrostatic discharge protection > 4,000 volts
• 8-pin PDIP/SOIC and 20-pin PLCC packages
• Data Retention > 200 years
• Temperature ranges:
- Commercial: 0°C to +70°C
- Industrial: -40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 37LV36/65/128 is a
family of Serial OTP EPROM devices organized inter-
nally in a x32 configuration. The family also features a
cascadable option for increased memory storage
where needed. The 37LV36/65/128 is suitable for
many applications in which look-up table information
storage is desirable and provides full static operation in
the 3.0V to 6.0V VCC range. The devices also support
the industry standard serial interface to the popular
RAM-based Field Programmable Gate Arrays (FPGA).
Advanced CMOS technology makes this an ideal boot-
strap solution for today's high speed SRAM-based
FPGAs. The 37LV36/65/128 family is available in the
standard 8-pin plastic DIP, 8-pin SOIC and 20-pin
PLCC packages.
Device Bits Programming Word
37LV36
37LV65
37LV128
36,288
65,536
131,072
1134 x 32
2048 x 32
4096 x 32
Xilinx is a registered trademark of Xilinx Corporation.
PACKAGE TYPES
PDIP
DATA 1
CLK 2
RESET/OE 3
CE 4
8 VCC
7 VPP
6 CEO
5 VSS
SOIC
DATA
CLK
RESET/OE
CE
PLCC
18
27
36
45
DATA VCC
VCC
VPP
CEO
VSS
CLK 4
5
RESET/OE 6
7
CE 8
18
17 VPP
16
15
14 CEO
Vss
BLOCK DIAGRAM
CE
RESET/OE
CEO
ADDRESS EPROM
Counter ARRAY
CLK
OE
DATA
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS21109E-page 1




37LV36-P pdf, 반도체, 판매, 대치품
37LV36/65/128
FIGURE 11-1: READ CHARACTERISTICS TIMING
CE
RESET/OE
TSCE
TSCED
CLK
DATA
TLC
TOE
TCE
TCAC
THCED
TSCE THCE
THC
THOE
TOH
TDF
TOH
TABLE 11-1: READ CHARACTERISTICS
AC Testing Waveform: VIL = 0.2V; VIH = 3.0V
AC Test Load: 50 pF
VOL = VOL_MAX; VOH = VOH_MIN
Symbol
Parameter
Limits 3.0V
Vcc 6.0V
Min. Max.
Limits 4.5V
Vcc 6.0V
Min. Max.
Units
Conditions
TOE OE to Data Delay
— 45 — 45
TCE CE to Data Delay
— 60 — 50
TCAC CLK to Data Delay
— 200 —
60
TOH Data Hold from CE, OE or CLK
0—0—
TDF CE or OE to Data Float Delay
— 50 — 50
TLC CLK Low Time
100 — 25 —
THC CLK High Time
100 — 25 —
TSCE
CE Set up Time to CLK
(to guarantee proper counting)
40 — 25 —
TSCED CE setup time to CLK
(to guarantee proper DATA read)
100 — 80 —
THCE
CE Hold Time to CLK
(to guarantee proper counting)
0—0—
THCED CE hold time to CLK
(to guarantee proper DATA read)
50 — 0 —
THOE
OE High Time
(Guarantees counters are Reset)
100
20 —
CLK max Clock Frequency
— 2.5 — 10
Note 1: This parameter is periodically sampled and not 100% tested.
2: Float delays are measured with output pulled through 1kto VLOAD = VCC/2.
ns
ns
ns
ns
ns Notes 1, 2
ns
ns
ns Note 1
ns
ns Note 1
ns
ns
MHz
DS21109E-page 4
© 1996 Microchip Technology Inc.

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37LV36-P 전자부품, 판매, 대치품
37LV36/65/128
TABLE 11-4: DC PROGRAMMING SPECIFICATIONS
Symbol Parameter
Ambient Temperature: Tamb = 25°C ±5°C
Limits
Min.
Max.
VCCP Supply voltage during programming
5.0
VIL Low-level input voltage
0.0
VIH High-level input voltage
2.4
VOL Low-level output voltage
VOH High-level output voltage
3.7
VPP1 Programming voltage*
12.5
VPP2 Programming Mode access voltage
VCCP
IPPP Supply current in Programming Mode
IL Input or output leakage current
-10
VCCL First pass Low-level supply voltage for final verification
2.8
VCCH Second pass High-level supply voltage for final verification
6.4
* No overshoot is permitted on this signal. VPP must not be allowed to exceed 14 volts.
6.0
0.5
VCC
0.4
13.5
VCCP+1
100
10
3.0
6.6
TABLE 11-5: AC PROGRAMMING SPECIFICATIONS (SEE NOTE 2)
Units
V
V
V
V
V
V
V
mA
µA
V
V
Symbol
Parameter
Limits
Min.
Max.
Units Conditions
TRPP 10% to 90% Rise Time of VPP
1 µs Note 1
TFPP 90% to 10% Fall Time of VPP
1 µs Note 1
TPGM VPP Programming Pulse Width
.50 1.05 ms
TSVC VPP Setup to CLK for Entering Programming Mode
100
ns Note 1
TSVCE CE Setup to CLK for Entering Programming Mode
100
ns Note 1
TSVOE OE Setup to CLK for Entering Programming Mode
100
ns Note 1
THVC VPP Hold from CLK for Entering Programming Mode
300
ns Note 1
TSDP Data Setup to CLK for Programming
50 ns
THDP Data Hold from CLK for Programming
0 ns
TLCE CE Low time to clear data latches
100 ns
TSCC CE Setup to CLK for Programming/Verifying
100
ns
TSIC OE Setup to CLK for Incrementing Address Counter
100
ns
THIC OE Hold from CLK for Incrementing Address Counter
0
ns
THOV OE Hold from VPP
200 ns Note 1
TPCAC CLK to Data Valid
400 ns
TPOH Data Hold from CLK
0 ns
TPCE CE Low to Data Valid
250 ns
Note 1: This parameter is periodically sampled and not 100% tested.
Note 2: While in Programming Mode, CE should only be changed while OE is HIGH and has been HIGH for 200 ns,
and OE should only be changed while CE is HIGH and has been HIGH for 200 ns.
© 1996 Microchip Technology Inc.
DS21109E-page 7

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