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부품번호 4030B 기능
기능 CMOS Quad Exclusive-OR Gate
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4030B 데이터시트, 핀배열, 회로
CD4030BMS
December 1992
CMOS Quad Exclusive-OR Gate
Features
Pinout
• High Voltage Type (20V Rating)
• Medium-Speed Operation
- tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current Of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
CD4030BMS
TOP VIEW
A1
B2
J=AB 3
K=CD 4
C5
D6
VSS 7
14 VDD
13 H
12 G
11 M = G H
10 L = E F
9F
8E
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Applications
• Even and Odd-Parity Generators and Checkers
• Logical Comparators
• Adders/Subtractors
• General Logic Functions
Description
The CD4030BMS types consist of four independent Exclu-
sive-OR gates. The CD4030BMS provides the system
designer with a means for direct implementation of the
Exclusive-OR function.
The CD4030BMS is supplied in these 14-lead outline pack-
ages:
Braze Seal DIP H4H
Frit Seal DIP
H1B
Ceramic Flatpack H3W
A1
B2
C5
6
D
E8
9
F
12
G
H 13
3J
4
K
10
L
11 M
J=AB
M=GH
K=CD
L=EF
VSS = 7
VDD = 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-317
File Number 3305




4030B pdf, 반도체, 판매, 대치품
Specifications CD4030BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Transition Time
Input Capacitance
SYMBOL
CONDITIONS
TTHL
TTLH
VDD = 10V
VDD = 15V
CIN Any Input
NOTES
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-
-
MAX
100
80
7.5
UNITS
ns
ns
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
VTN VDD = 10V, ISS = -10µA
VTP
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
7.5
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 0.2µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
7-320

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4030B 전자부품, 판매, 대치품
CD4030BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF
300
200
100
0 5 10 15 20
SUPPLY VOLTAGE (VDD) (V)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNC-
TION OF SUPPLY VOLTAGE
105 6
4
AMBIENT TEMPERATURE (TA) = +25oC
2
104 6
4
2
103 6
4
2
102 6
4
2
SUPPLY VOLTAGE
(VDD) = 15V
10V
10V
10
6
4
2
16
4
2
10-1
2
10-1
4 68 2
1
5V
LOAD CAPACITANCE
CL = 50pF
CL = 15pF
4 68 2 4 68 2 4 68 2 4 68
10 102 103 104
INPUT FREQUENCY (fI) (kHz)
FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11kÅ 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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