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PDF LV2105V Data sheet ( Hoja de datos )
| Número de pieza | LV2105V | |
| Descripción | 530 MHz PLL Frequency Synthesizer LSI | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number: EN4876B
Bi-CMOS LSI
LV2105V
530 MHz PLL Frequency Synthesizer LSI
Overview
The LV2105V is a PLL frequency synthesizer Bi-CMOS LSI
that provides low-voltage operation and low current drain, and
that is suitable for use in a variety of radio equipment.
Package Dimensions
unit: mm
3178-SSOP16
[LV2105V]
Functions
. PLL function
. Data input by serial transfer (CCB format)
. Input amplifier for crystal oscillation circuit
. Data output port
Features
. Low operating voltage: (VCC = 2.5 to 5.5 V)
. Low current drain (5.5 mA)
. Compact package (SSOP16, 0.65 mm pitch)
. VCO band switching data output port on chip
. Data can be input while in power saving mode
. Data input pin high level can be input at VCC or higher
. Independent setting of CP ON/OFF (high impedance)
possible
SANYO : SSOP16
. CCB is a trademark of SANYO ELECTRIC CO., LTD.
. CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Specifications
Absolute Maximum Ratings at Ta = 25 °C
Parameter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Maximum output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VCC max
VIN max(1)
VIN max(2)
VOUT max(1)
VOUT max(2)
IOUT max
Pd max
Topr
Tstg
Conditions
VCCR, VCCD
CE, CL, DI
XIN, TEST
PDP
PDN, OUT, PE
PDP
114 × 76 × 1.6 mm3
When using glass epoxy board
Ratings
–0.3 to +6.0
–0.3 to +6.0
–0.3 to VCC+0.3
–0.3 to +9.0
–0.3 to VCC+0.3
0 to +1.0
230
–40 to +85
–50 to +125
Unit
V
V
V
V
V
mA
mW
°C
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
D3095HA(II) No.4876-1/7
1 page  
LV2105V
Continued from preceding page.
Pin No.
(3)
Control block/data
Power save data
PS
. Internal block
Data that sets the power save mode on or off
PS data
Item
0 Power save mode
1 Normal operation
.(4)
Output port data
Data that sets the output of the output port
OUT
OUT data OUT Pin
0 Low
1 High
.(5)
Charge pump ON/OFF data
Data that sets whether to operate the charge pump or to implement
CP high impedance.
CP data
Item
0 High impedance
1 Normal operation
.(6)
LSI test data TS1
LSI test mode switch.
. Set TS1 = 0. Normally, the TEST pin is connected to GND.
(7)
Programmable divider data
Data that sets the division ratio of the programmable divider.
FP0 to FP16
Binary value with FP0 as the LSB. However, the settable division ratio
factor is up to 131071.
Pin Functions
Pin Name
1 XIN
2 CL
3 DI
4 CE
5 VCCR
6 PI
7 GND R
8 TEST
9 CP
10 PDP
11 PDN
12 GND D
13 VCCD
14 PE
15 OUT
16 XOUT
Pin Function
Reference signal input pin (Xtal oscillation pin)
Data input pin
Data input pin
Data input pin
ECL block power supply pin
Comparison signal input pin
ECL block GND pin
LSI test pin. Must be connected to GND.
Built-in charge pump output pin
Phase comparator output for an external charge
pump.
If not to be used, connect to GND.
Phase comparator output for an external charge
pump.
GND pin for circuits except the ECL block
Power supply pin for circuits except the ECL block
Phase error output pin for phase comparator
Output port pin for switching external SW.
Output pin for Xtal oscillation
I/O Style
CMOS input
CMOS, No pull-down
CMOS, No pull-down
CMOS, No pull-down
BIP input
CMOS, No pull-down
BIP
CMOS, Nch open-drain output
CMOS output
CMOS output
BIP NPN open-collector output
CMOS output
No.4876 -5/7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LV2105V.PDF ] | |
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