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PDF LVT162245 Data sheet ( Hoja de datos )
| Número de pieza | LVT162245 | |
| Descripción | Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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January 1999
Revised November 1999
74LVT162245 • 74LVTH162245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
and 25Ω Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen non-
inverting bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVT162245 and LVTH162245 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
The LVTH162245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) VCC applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT162245
and LVTH162245 are fabricated with an advanced BiC-
MOS technology to achieve high speed operation similar to
5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V
VCC
s Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
s Live insertion/extraction permitted
s Power Up/Down high impedance provides glitch-free
bus loading
s A Port outputs include equivalent series resistance of
25Ω making external termination resistors unnecessary
and reducing overshoot and undershoot
s A Port outputs source/sink ±12 mA. B Port outputs
source/sink −32 mA/+64 mA
s Functionally compatible with the 74 series 162245
s Latch-up performance exceeds 500 mA
Ordering Code:
Order Number
Package
Number
Package Description
74LVT162245MEA
(Note 1)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LVT162245MTD
(Note 1)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
[TUBE]
74LVTH162245MEX
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
[TAPE and REEL]
74LVTH162245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
74LVTH162245MTX
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 2: Use this Order Number to receive devices in Tape and Reel.
© 1999 Fairchild Semiconductor Corporation DS012446
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
TA = −40°C to +85°C
CL = 50 pF, RL = 500Ω
VCC = 3.3V ± 0.3V
VCC = 2.7V
Min Max Min Max
Units
tPLH Propagation Delay Data to A Port Output
tPHL
1.0 4.0 1.0 4.6
ns
1.0 3.7 1.0 4.1
tPLH Propagation Delay Data to B Port Output
tPHL
1.0 3.5 1.0 3.9
ns
1.0 3.5 1.0 3.9
tPZH Output Enable Time for A Port Output
tPZL
1.0 5.3 1.0 6.3
ns
1.0 5.6 1.0 7.2
tPZH Output Enable Time for B Port Output
tPZL
1.0 4.6 1.0 5.4
ns
1.0 5.3 1.0 6.9
tPHZ Output Disable Time for A Port Output
tPLZ
1.5 5.6 1.5 6.3
ns
1.5 5.5 1.5 5.5
tPHZ Output Disable Time for B Port Output
tPLZ
1.5 5.4 1.5 6.1
ns
1.5 5.1 1.5 5.4
tOSHL
tOSLH
A Port Output to Output Skew
(Note 11)
1.0 1.0 ns
tOSHL
tOSLH
B Port Output to Output Skew
(Note 11)
1.0 1.0 ns
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance (Note 12)
Symbol
Parameter
Conditions
CIN Input Capacitance
VCC = 0V, VI = 0V or VCC
CI/O
Input/Output Capacitance
VCC = 3.0V, VO = 0V or VCC
Note 12: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
Typical
4
8
Units
pF
pF
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LVT162245.PDF ] | |
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