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부품번호 LX1688IPW 기능
기능 MULTIPLE LAMP CCFL CONTROLLER
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LX1688IPW 데이터시트, 핀배열, 회로
RangeMAX™
LX1688
INTEGRATED PRODUCTS
MULTIPLE LAMP CCFL CONTROLLER
DESCRIPTION
The LX1688 is a fixed frequency,
dual current/voltage mode, switching
regulator that provides the control
function for Cold Cathode Fluorescent
Lighting (CCFL). This controller can
be used to drive a single lamp, but is
specifically designed for multiple lamp
LCD panels. The IC can be configured
as a master or slave and synchronize up
to 12 controllers.
The LX1688 includes highly
integrated universal ‘PWM or DC’
dim input that allows either a PWM or
DC input to adjust brightness without
requiring external conditioning, since a
single external capacitor CPWM can
be used to integrate a PWM input.
Burst mode dimming is possible if the
user supplies a low frequency PWM
signal on the BRITE input and no
CPWM capacitor is used. The
controller utilizes Linfinity’s patented
direct drive fixed frequency topology
and patented resonant lamp strike
generation technique.
Safety and reliability features
include a dual feedback control loop that
permits regulation of maximum lamp
strike voltage as well as lamp current.
Regulating maximum lamp voltage
permits the designer to provide for ample
worst-case lamp strike voltage while
conservatively limiting maximum open
circuit voltage. In addition the controller
features include auto shutdown for an
open or broken lamp, and a lamp fault
detection with a status reporting output.
To improve design flexibility the IC
includes the ability to select the polarity
of both the chip enable and dim (BRITE)
inputs. Also included is a switched VDD
output of up to 10mA that will allow the
user to power other circuitry that can be
switched on and off with the inverters
enable input. This preserves the micro
power sleep mode with no additional
components.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
PRODUCT HIGHLIGHT
DIM M ING (BRITE)
ENABLE
LAMPS
IN PUT
CONNECTOR
LX1688
MASTER
KEY FEATURES
ƒ Provision to synchronize lamp
current & frequency with other
controllers
ƒ Dimming with analog or digital
(PWM) methods (>20:1)
ƒ Programmable Fixed frequency
ƒ Adjustable Power-up reset
ƒ ENABLE/BRITE Polarity Selection
ƒ Voltage limiting on step-up
transformer secondary winding
ƒ Open lamp timeout circuitry
ƒ Switched VDD output (10mA)
ƒ Micro-Amp Sleep Mode
ƒ Operates with 3.3V to 5V Supply
ƒ 100mA output drive capability
APPLICATIONS/BENEFITS
ƒ Desktop LCD Monitors
ƒ Multiple lamp panels
ƒ Low Ambient Light Displays
ƒ High Efficiency
ƒ Lower Cost than Conventional
Buck/Royer Inverter Topologies
ƒ Improved Lamp Strike Capability
ƒ Improved Over-Voltage Control
FAULT 1
FAULT 2
Copyright 2001
Rev. 1.1a, 2003-03-21
FAULT 1
ENABLE
BRITE
STRIKE
STATUS
125 Hz 5% Duty cycle Burst
65KHz run frequency
LX1688
SLAVE
VDD
FAULT 2
S T R IK E
STATUS
Ch3 10.0mV
Ch2 10.0mV M 100µs
Simplified quad lamp inverter showing synchronized output waveforms
TJ (°C)
0 to 70
-40 to 85
PACKAGE ORDER INFO
MIN VDD
PWMAX VDD
Plastic TSSOP
24-Pin
3.0V
5.5V
LX1688CPW
3.0V
5.5V
LX1688IPW
Microsemi
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 1




LX1688IPW pdf, 반도체, 판매, 대치품
RangeMAX™
LX1688
INTEGRATED PRODUCTS
MULTIPLE LAMP CCFL CONTROLLER
ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter
Strike and Ramp Generator (continued)
Minimum PHA_SYNC-pin output current
Minimum RMP_RST-pin output current
Minimum A_SYNC output pulse duty-cycle
Minimum A_SYNC input pulse duty-cycle
Minimum RMP_RST output pulse duty-cycle
Minimum RMP_RST input pulse duty-cycle
Output Buffer
Output Sink Current
Output Source Current
Output Sink Current
Output Source Current
Output Sink Current
PWM
VSNS threshold voltage
VCOMP Discharge Current
IAMP transconductance
VAMP, IAMP output source current
VAMP, IAMP output sink current
ICOMP discharge current
VAMP transconductance
ICOMP-to-output propagation delay
BIAS
Voltage at Pin I_R
Pin I_R max. source current
Power-on Reset Pulse Width
Minimum VDDSW sourcing Current
VDDSW Off Current
General
Operating Current
Output buffer operating current
ENABLE logic threshold
ENABLE threshold hysteresis
Sleep-mode current (see table-1 for Pin
ENABLE polarity)
VDD_P Leakage in Sleep Mode
UVLO threshold
UVLO hysteresis
Symbol
Test Conditions
I_PHA_SYNC
I_RMP_RST
DO_ASYNC
DI_ASYNC
DO_RST
DI_RST
ISK_OUTBUF
IS_OUTBUF
ISK_OUTBUF
IS_OUTBUF
ISK_OUTBUF
VSLAVE = 0V
VSLAVE = 0V
VSLAVE = 0V
VSLAVE = VDD
VSLAVE = 0V
VSLAVE = VDD
VAOUT, BOUT = 1V
VDD = 5.5V
VAOUT, BOUT = 4.5V
VDD = 5.5V
VAOUT, BOUT = 1V, VDD = 3V
VAOUT, BOUT = 2V, VDD = 3V
VAOUT, BOUT = 1V, VDD = 5.5V
VTH_VSNS
ID_VCOMP
GM_IAMP
IS_IAMP
ISK_IAMP
ID_ICOMP
GM_ICMP
TD_ICOMP
ISNS = 0.2V
VCOMP, ICOMP = 0
VCOMP, ICOMP =VDD
VSNS = 0.1V
V_IR
IMAX_IR
TPOR
IMIN_VDDSW
IOFF_VDDSW
IDD
IDD_P
VTH_EN
VTH_EN
IDD_SLEEP
IDD_SLEEP
IDD_SLEEP
IDD_SLEEP
VTH_UVLO
VH_UVLO
CPOR =.1uF
(VDD – VDDSW) < 0.2V
VENABLE = 0.8V, VBEPOL = VDD
VDDSW = 0V
VDD = VDD_P = 5V
VOLSNS = VDD = VDD_P = 5V,
CA = CB = 1000pF
VENABLE = 0.8V
(VBEPOL = VDD or float)
VENABLE = 2.5V
(VBEPOL = VDD or float)
VENABLE = 0.8V
(VBEPOL = VSS)
VENABLE = 2.5V
(VBEPOL = VSS)
Rising turn-on threshold
Falling turn-off hysteresis
LX1688
Min Typ.
10
10
49 50
48 50
10 17
5
100
100
50
50
100
1.2 1.25
4
100 200
75
75
10
200 500
1100
0.95
50
31
10 25
1
5.5
2
0.8 1.7
0.2
20
20
20
20
2.6 2.8
190
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Max Units
‘mA
mA
%
%
%
%
‘mA
‘mA
‘mA
‘mA
‘mA
1.3 V
‘mA
500 µmho
µA
µA
‘mA
800 µmho
nS
1.05 V
µA
mS
‘mA
15 µA
8 mA
4 mA
2.4 V
V
50
50
µA
300
300
2.9 V
mV
Page 4

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LX1688IPW 전자부품, 판매, 대치품
RangeMAX™
LX1688
INTEGRATED PRODUCTS
MULTIPLE LAMP CCFL CONTROLLER
DETAILED DESCRIPTION
The LX1688 is a backlight controller specifically
designed with a special feature set needed in multiple
lamp desktop monitors, and other multiple lamp displays.
While utilizing the same architecture as Linfinity’s
LX1686 controller it eliminates the synchronized digital
dimming and adds, lamp ‘strike’ count out timer, lamp
fault status output, and external clock input/output that
permits multiple controllers to synchronize their output
current both in frequency and phase.
Operation From 3.3V and/or 5.0V Input Supply
The LX1688 is designed to operate and meet all
specifications at 3.3V ±10% to 5.0V ±10%. The under
voltage lockout is set at nominally 2.8V with a 190mV
hysteresis.
Master/Slave Clock Synchronization
One or more controllers (up to 11) may be designated
as slave controllers and receive ramp reset and phase
synchronization from the designated master controller.
This will allow up to 12 lamps (24 with two lamps in
series/controller design) to all operate in phase and
frequency synchronization. This is important to prevent
random interference between lamps through
unpredictably changing electric and magnetic fields that
will inevitably link them.
The LX1688 has two independent oscillators, one for
lamp strike and one for the lamp run frequency. The
strike oscillator ramps the operating frequency slowly up
and down when the open lamp sense input (OLSNS)
indicates the lamp is not ignited. During this lamp strike
condition the operating frequency of each IC will vary up
and down as needed to strike its lamp. The controller is
so designed that the master controller clock remains at the
pre-selected frequency for fully ignited lamps even while
striking. Likewise the designated slave controller will not
alter the frequency or phase of the master clock during its
strike phase. Thus each controller will vary its frequency
as needed to strike its lamp then it will synchronize to the
master clock frequency and phase.
The TRI_C wave generator (see Block Diagram) sets
the rate of operating frequency variation during lamp
strike. The TRI_C generator is connected to a 6-bit
counter that times out after 63 cycles and then latches the
FAULT output high if the OLSNS input indicates no
lamp current is flowing. Even in the case of timeout fault
the master controller clock will continue to provide
synchronization to the slave controllers.
When synchronizing more than one controller the
Ramp Reset (RMP_RST), Phase Sync (PHA_SYNC),
and Slave Input/Output are used. RMP_RST and
PHA_SYNC should be connected between all the
controllers. The master controller should have its SLAVE
pin connected to VSS (GND) and the slave controllers
SLAVE input to VDD (High).
BEPOL Input
The BEPOL pin is a tri-mode input that controls the
polarity of the ENABLE and BRITE input signals.
Depending on the state of this pin (VDD, floating, or VSS)
the controller can be set to allow active high enable with
active high full brightness or active high or low enable with
active low full brightness (see Table 1).
BRITE Input (Dimming Input)
The BRITE input is capable of accepting either a DC
voltage (.5V to 2.5V) or a PWM digital signal that is
clamped on chip (<.5V or >2.5V). A digital signal can
either be passed unfiltered to effect pulse ‘digital’ dimming
or filtered with a capacitor to effect analog dimming with a
digital PWM signal.
Analog Dimming Methods:
Mechanical or digital potentiometer set to provide 1V
to 2.5V on the wiper output. A filter cap from BRITE
to signal ground is recommended.
D/A converter output directly connected to BRITE
input. A R/C filter using a capacitor from the CPW1
input to ground for applications where the ADC
output may contain noise sufficient to modulate the
BRITE input.
A high frequency PWM digital logic pulse connected
directly to the BRITE input. The Brightness (BRT,
internal node) output will be sensitive only to the
PWM duty cycle, and not to the PWM signal
amplitude, so long as the amplitude exceeds 2.6V for
a logic high (1) and is less than .4V for a logic (0).
This pulse frequency will typically be between 1KHz
and 100KHz and will not be synchronized with the
LCD video frame rate. A capacitor (CPWM) between
CPW1 and CPW2 will integrate the PWM signal for
use by the controller.
Digital Dimming Methods:
Low frequency PWM digital logic pulses connected
directly to the BRITE input. As above the Brightness
(BRT internal) will be sensitive only to the PWM
duty cycle, and not to the PWM signal amplitude, so
long as the amplitude exceeds 2.6V for a logic high
(1) and is less than .4V for a logic (0). This pulse
frequency will typically be in the range of 90-320Hz
Copyright 2001
Rev. 1.1a, 2003-03-21
Microsemi
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
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LX1688IPW

MULTIPLE LAMP CCFL CONTROLLER

Microsemi Corporation
Microsemi Corporation

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