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PDF LXT6234 Data sheet ( Hoja de datos )
| Número de pieza | LXT6234 | |
| Descripción | E-Rate Multiplexer | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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LXT6234
E-Rate Multiplexer
Datasheet
The LXT6234 E-Rate Multiplexer is a single-chip solution for multiplexing four tributary
channels into a single high speed data stream and for demultiplexing a high speed data stream
back to four tributary channels. All of the necessary circuitry is integrated into the LXT6234 E-
Rate Multiplexer; there is no need for an external framing device.
The LXT6234 E-Rate Multiplexer conforms to both the (ITU) G.742 and (ITU) G.751
multiplexing formats defined by the International Telecommunications Union (ITU; formerly
known as CCITT): G.742 recommendation for multiplexing four E1 channels into an E2 frame;
and the G.751 recommendation for multiplexing four E2 channels into an E3 frame.
The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding
used on E1, E2, and E3 signals. The coder and decoder input/output pins are externally
accessible, allowing either HDB3 or NRZ (non-return-to-zero) I/O to the multiplexer. The
LXT6234 E-Rate Multiplexer can also serve as a five channel HDB3 coder and decoder.
Applications
n E1/E2 Multiplexer (2/8 Mbit/s)
n E2/E3 Multiplexer (8/34 Mbit/s)
n E1/E3 Multiplexer (2/34 Mbit/s)
Product Features
n Digital Loop Carrier (DLC) Terminal
n Add / Drop Multiplexers (ADM)
n 4 - to - 1 Non-Standard Multiplexer
n Performs four-E1 to one-E2, or four-E2 to
one-E3 multiplexing. Five ICs will
implement a sixteen-E1 to one-E3
multiplexer.
n Fully compliant with the G.742 and G.751
ITU recommendations. Fully compliant
with G.703 when used with LXT305/332
Line Interface.
n A robust frame-acquisition and frame-
holding algorithm minimizes frame
slippage, acquires and holds frame below
10-2 bit error rate.
n Four auxiliary low speed data or flag
channels are available via the Stuffing Bits
on each tributary channel.
n Access to the Alarm bit and the National
bit. These can be used as recommended by
ITU or for proprietary use.
n Five independent HDB3 CODECs allow
multiplexer I/O in either HDB3 or NRZ
formats. The LXT6234 can also function as
a stand alone five-channel HDB3
transcoder.
As of January 15, 2001, this document replaces the Level One document
LXT6234 E-Rate Multiplexer Datasheet.
Order Number: 249301-001
January 2001
1 page  
E-Rate Multiplexer — LXT6234
1.0 Block Diagram
Figure 1. Block Diagram
High Speed NRZ Data Input
Clock
Mode Select
HDB3 Data Input
Clock
4 Tributary NRZ Data Inputs
4 Clocks
4
4
Demultiplexer
Demultiplexer
And
Timing
Control
HDB3 Decoder
HDB3
Encoder #[1:4]
4
4
6
8
4 HDB3 Pos/Neg Data Input Pair8s
4 Clocks
4
4 Force AIS 4
4
4 NRZ Data Inputs
Service Channels / Ref Clock 4
High Speed Multiplexer Clock
NRZ Data Input
Clock
Multiplexer
HDB3
Decoder #[1:4]
4
4
4
Elastic Store
Multiplexer
And
Timing
Control
HDB3 Encoder
2
4 Tributary NRZ Data Outputs
4 Clocks
Loss Of Signal (LOS)
Service Channels / AIS
NRZ Data Output
Bipolar Violation Alarm
4 HDB3 Pos/Neg Data Output P
4 NRZ Data Outputs
4 Bipolar Violation Alarms
4 Elastic Store Alarm Indication
High Speed NRZ Data Output
Frame Sync Pulse
Pos/Neg Data Output Pair
Datasheet
5
5 Page 
3.0
3.1
3.2
E-Rate Multiplexer — LXT6234
Functional Description
The LXT6234 E-Rate Multiplexer consists of a multiplexer block, a demultiplexer block, five
HDB3 decoders, and five HDB3 encoders. If the HDB3 codecs are used, the signal flow would be
as follows:
Multiplexer: Four tributaries of data feed HDB3 decoders one through four. The NRZ outputs of
the decoders are connected to the multiplexer tributary inputs. Within the multiplexer, the
justification or stuffing for each tributary is determined; the frame word is added; and the high
speed NRZ data sent out. The multiplexer output is connected to HDB3 encoder five where it is
encoded and sent out as Positive Data Output (MHDPO) and Negative Data Output (MHDNO).
Demultiplexer: High speed encoded data feeds the HDB3 decoder five and is output as NRZ data.
The decoder output is connected to the demultiplexer input where it enters both the frame search
circuitry and the demultiplexing circuitry. Once the frame is detected, the NRZ data is
demultiplexed into the four tributaries and the justification is removed. Tributary data is then sent
out in NRZ format. These tributary outputs, both Clock Output (DLCOx) and NRZ Output
(DLNRZOx), are connected to HDB3 encoders one through four, encoded, and output as Positive
Data (MHDPO) and Negative Data (MHDNO).
Frame Format
The multiplexer and demultiplexer share the Mode Select (MODE) control pin. When MODE is
low, the multiplexer conforms to the ITU G.742 format for four-E1 to E2 (Figure 4). An E2 frame
is 848 bits long, with 205 data bits and one justification bit for each E1 tributary. When MODE is
high, the multiplexer conforms to the ITU G.751 format for four-E2 to E3 (Figure 5). This E3
frame is 1536 bits long, with 377 data bits and one justification bit for each E2 tributary.
In both E2 and E3 formats, there are two flag bits per frame: the AIS bit and the National bit. The
four justification bits may also be used as additional flag bits.
HDB3 Codecs
Five HDB3 codecs are included within the LXT6234 to allow easy integration with a wide range of
line interface circuits. There are four low speed codecs for the tributary streams and one high speed
codec to process the high speed output data. All five codecs are identical and all I/O pins are
externally accessible for each device. All codecs can be operated at the maximum operating speed
if the chip is used as a stand alone HDB3 transcoder. Note that the "low speed" decoders share a
clock with the multiplexer tributary clocks.
Each HDB3 decoder is provided with Positive Data, Negative Data, and clock; they decode the
data into a single NRZ bit stream. The HDB3 encoders are provided with NRZ data and clock; they
produce the Positive Data and Negative Data bit streams.
Datasheet
11
11 Page | ||
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