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PDF LZ93N19 Data sheet ( Hoja de datos )
| Número de pieza | LZ93N19 | |
| Descripción | Synchronous Signal Generator for CCD | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LZ93N19
LZ93N19
Synchronous Signal Generator for CCD
DESCRIPTION
The LZ93N19 is a CMOS synchronous signal
generator LSI which provides TV synchronous
pulses and video signal processing pulses, in
combination with the timing signal generator LSI
(LZ93N61, LZ93F50, LZ93F33 or LZ95D37/M).
FEATURES
q Switchable between 270000 pixels CCD and
320000 pixels CCD
q Switchable between NTSC (EIA) and PAL
(CCIR) systems
q Single +5 V power supply
q External synchronization is possible
q Package : 44-pin QFP(QFP044-P-101 O)
BLOCK DIAGRAM
PIN CONNECTIONS
44-PIN QFP
TOP VIEW
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{
VD 34
FI 35
CPBL 36
BCPI 37
BCP2 3s
PBLK 39
HG I 40
HG2 41
WBLK 42
4FSC z
TST I 44
0
~ll121131[4115f16f17f18f19
101II
o~u $~p;ufil~mnoZn3xE>mkJpm~z
22 CKMD
21 TST2
20 FRP I
19 FRP2
18 TST5
17 CSYNC
16 CBLK
15 ENCP
14 LSW
13 LRST
12 TVMD
/
CLKI
CKMD
VRI
CFMI
4FSC
Vcc
GND
GND
TSTI TST2 TST3 TST4 TST5
S C H D TVMD SC~ S C 2 RPI
CPMD
HG I
HG2
CPBL
WHD
BF
ENCP
CBLK
CSYNC
HBLK
HD
BCP I
BCP2
PBLK
WBLK
CFMO
BFBL
LSW
FRP2
FRP I
VD
FI
Em
CPI
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1 page  
LZ93N19
~:. SYMBOL
27 CLKI
28 Vcc
29 EOO
30 CPI
31 HD
32 RPI
33 SCHD
34 VD
35 FI
36 CPBL
1/0 POIARITY
PIN NAME
Ic nr Main clock
FUNCTION
An input pin for reference clock,
tinnect to DOUT (pin 3) of timing LSI (U93N61 ) or
DO (pin 3) of timing LSI; following frequencies ap-
pear on this pin;
At NT3C mode : 9.534964 MHz when CKMD = L level
12.713285 MHzwhen CKMD = H level
At PAL mode : 9.656250 MHz when CKMD = L level
12.875 ~ MHz when CKMD = H level
— — Power supply
Supply +5 V Wwer.
Phase comparator output for input signals RPI (pin
TO
—
Phase comparator
output
32) and CPI (pin 30). When CPI is advanced, output
is Low level. When CPI is delayed, output is High
level, When phases are equal, the terminal imped-
ance is High.
An input pin for comparison horizontal signal to the
Horizontal comparison phase comparator. Connect to SCHD (pin 33) when
Ic – input
comparator is used. Set to L level when comparator
is not used.
o
n
Horizontal drive pulse
The pulse occurs at the start of lines. Connect to
timing LSI.
An input pin for the reference horizontal signal to
Ic
Horizontal reference the phase comparator. Connect to HD (pin 31) when
n input
comparator is used, Set to L level when comparator
is not used.
o n Subcarrier HD
A horizontal synchronization pulse obtained by di-
viding 4FSC (pin 43).
At NTSC mode : dividing into 1 /91 O 4FSC.
At PAL mode : dividing into 1/} 135 4FSC ordi-
narily and dividing into 1/1 137
4FSC during one horizontal pe-
riod within the V blanking,
0 n V drive pulse
The pulse occurs at the start of every field. Con-
nect to VDI (pin 2) of timing LSI (LZ93N61 ) or VDI
(Pin 1) of timing LSI (U92E62).
o N Filed index
The pulse is used for detecting field.
At NTSC mode : 1st field; LOW
2nd field; HIGH
At PAL mode : 1st and 3rd field; LOW
2nd and 4th field; HIGH
Ic
When the input is High, BCPI (pin 37) and BCP2
n
Blanking clamp pulse
(pin 36) are Low.
5 Page 
LZ93N19
(ODD FtELD)
“WBLK”, “CBLK” TIMING < NTSC >
Unit : ps
492 493
525 1
;+- ,L
~“WBLK
118.5 H+ 18.88 PS
‘~
(EVEN FIELD)
CBLK
230 231 232
~,
263
n
264 349 350 351
PO ,—x~
~’WBLK
118.5 H+7.87 US
‘~
“WBLK” , “CBLK” TIMING < PAL >
(Ist, 3rd FIELD)
586
%7 W
C B L K _n_n_n—,
623
n
624 100 101
25 H~~
~’WBLK
137.5 H +20.51 U S
(2nd, 4th HELD)
CBLK
274 275 276 310
311
336 412 413 414
~~+~~
WBLK ~
137.5 H +8.39 X5
“~
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet LZ93N19.PDF ] | |
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