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M-8870-02SM 데이터시트 PDF




Clare Inc.에서 제조한 전자 부품 M-8870-02SM은 전자 산업 및 응용 분야에서
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부품번호 M-8870-02SM 기능
기능 DTMF Receiver
제조업체 Clare Inc.
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M-8870-02SM 데이터시트, 핀배열, 회로
Features
Low Power Consumption
Adjustable Acquisition and Release Times
Central Office Quality and Performance
Power-down and Inhibit Modes (-02 only)
Inexpensive 3.58 MHz Time Base
Single 5 Volt Power Supply
Dial Tone Suppression
Applications
Telephone switch equipment
Remote data entry
Paging systems
Personal computers
Credit card systems
Pin Configuration
Block Diagram
M-8870
DTMF Receiver
Description
The M-8870 is a full DTMF Receiver that integrates
both bandsplit filter and decoder functions into a single
18-pin DIP or SOIC package. Manufactured using
CMOS process technology, the M-8870 offers low
power consumption (35 mW max) and precise data
handling. Its filter section uses switched capacitor
technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting
techniques to detect and decode all 16 DTMF tone
pairs into a 4-bit code. External component count is
minimized by provision of an on-chip differential input
amplifier, clock generator, and latched tri-state inter-
face bus. Minimal external components required
include a low-cost 3.579545 MHz color burst crystal, a
timing resistor, and a timing capacitor.
The M-8870-02 provides a “power-down” option
which, when enabled, drops consumption to less
than 0.5 mW. The M-8870-02 can also inhibit the
decoding of fourth column digits (see Tone Decoding
table on page 5).
Ordering Information
Part #
M-8870-01
Description
18-pin plastic DIP
M-8870-01SM 18-pin plastic SOIC
M-8870-01SMTR 18-pin plastic SOIC, tape and reel
M-8870-02
18-pin plastic DIP, power-down,
option
M-8870-02SM
18-pin plastic SOIC, power-down,
option
M-8870-02T
18-pin plastic SOIC, power-down
option, tape and reel
DS-M8870-R3
www.clare.com
1




M-8870-02SM pdf, 반도체, 판매, 대치품
M-8870
Pin Functions
Pin Name
Description
1 IN+ Non-inverting input
Connections to the front-end differential amplifier.
2 IN- Inverting input
3 GS Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
4 VREF Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
5 INH* Inhibits detection of tones representing keys A, B, C, and D.
6 PD* Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
7 OSC1 Clock input
3.579545 MHz crystal connected between these pins completes the internal oscillator.
8 OSC2 Clock output
9 VSS Negative power supply (normally connected to 0 V).
10 OE Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
11-14 Q1, Q2, Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair
Q3, Q4 received (see Tone Decoding table on page 5).
15 StD Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below VTSt.
16 ESt Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal
condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17 St/GT Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT
output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See
Common Crystal Connection on page 5).
18 VDD Positive power supply. (Normally connected to +5V.)
* -02 only. Connect to VSS for -01 version
Guard Time Adjustment
Where independent selection of signal duration and
interdigit pause are not required, the simple steering
circuit of Basic Steering Circuit is applicable.
Component values are chosen according to the formu-
la:
tREC = tDP + tGTP
tGTP @ 0.67 RC
The value of tDP is a parameter of the device and
tREC is the minimum signal duration to be recognized
by the receiver. A value for C of 0.1 µF is recommend-
ed for most applications, leaving R to be selected by
the designer. For example, a suitable value of R for a
tREC of 40 ms would be 300 k. A typical circuit using
this steering configuration is shown in the Single -
Ended Input Configuration on page 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrange-
ments may be used to select independently the guard
times for tone-present (tGTP) and tone-absent (tGTA).
This may be necessary to meet system specifications
that place both accept and reject limits on both tone
duration and interdigit pause.
registered. On the other hand, a relatively short tREC
with a long tDO would be appropriate for extremely
noisy environments where fast acquisition time and
immunity to dropouts would be required. Design infor-
mation for guard time adjustment is shown in the
Guard Time Adjustment below.
Power-down and Inhibit Mode (-02 only)
A logic high applied to pin 6 (PD) will place the device
into standby mode to minimize power consumption. It
Figure 5 Guard Time Adjustment
Guard time adjustment also allows the designer to tai-
lor system parameters such as talkoff and noise immu-
nity. Increasing tREC improves talkoff performance,
since it reduces the probability that tones simulated by
speech will maintain signal condition long enough to be
4
www.clare.com
Rev. 3

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M-8870-02SM 전자부품, 판매, 대치품
Timing Diagram
M-8870
Explanation of Events
(A) Tone bursts detected, tone duration invalid, outputs not updated.
(B) Tone #n detected, tone duration valid, tone decoded and latched in outputs.
(C) End of tone #n detected, tone absent duration valid, outputs remain latched until next valid tone.
(D) Outputs switched to high impedance state.
(E) Tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance).
(F) Acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched.
(G) End of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone.
Explanation of Symbols
VIN
ESt
St/GT
Q1 - Q4
StD
OE
tREC
tREC
tID
tDO
tDP
tDA
TGTP
TGTA
DTMF composite input signal.
Early steering output. Indicates detection of valid tone frequencies.
Steering input/guard time output. Drives external RC timing circuit.
4-bit decoded tone output.
Delayed steering output. Indicates that valid frequencies have been present/
absent for the required guardtime, thus constituting a valid signal.
Output enable (input). A low level shifts Q1 - Q4 to its high impedance state.
Maximum DTMF signal duration not detected as valid.
Minimum DTMF signal duration required for valid recognition.
Minimum time between valid DTMF signals.
Maximum allowable dropout during valid DTMF signal.
Time to detect the presence of valid DTMF signals.
Time to detect the absence of valid DTMF signals.
Guard time, tone present.
Guard time, tone absent.
Rev. 3 www.clare.com
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관련 데이터시트

부품번호상세설명 및 기능제조사
M-8870-02SM

DTMF Receiver

Clare  Inc.
Clare Inc.

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