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M-986-1R2P 데이터시트 PDF




Clare Inc.에서 제조한 전자 부품 M-986-1R2P은 전자 산업 및 응용 분야에서
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부품번호 M-986-1R2P 기능
기능 MFC Transceivers
제조업체 Clare Inc.
로고 Clare  Inc. 로고


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M-986-1R2P 데이터시트, 핀배열, 회로
Features
Direct A-Law PCM digital input
2.048 Mb/s clocking
Programmable forward/backward mode
Programmable compelled/direct control
Operates with standard codecs for analog
interfacing
Microprocessor read/write interface
Binary or 2-of-6 data formats
Single- or dual-channel versions
5 volt power
Applications
Test equipment
Trunk adapters
Paging terminals
Traffic recorders
PBXs
Pin Assignments
Block Diagram
M-986-2R2
MFC Transceivers
Description
The M-986-1R2 and -2R2 MFC Transceivers contain
all the logic necessary to transmit and receive CCITT
R2F (forward) and R2B (backward) multifrequency
signals on one 40-pin integrated circuit (IC). M-986-
1R2 is a single-channel version; M-986-2R2 provides
two channels. R1 single and dual multifrequency
transceivers are also available as M-986-1R1 and -
2R1.
Operating with a 20.48 MHz crystal, the M-986 is
capable of providing a direct digital interface to an A-
law-encoded PCM digital input. Each channel can be
connected to an analog source using a coder-decoder
(codec) as shown in the Block Diagram below.
The M-986 can be configured by the customer to
operate with the transmitter and receiver either cou-
pled together or independently, allowing it to handle a
compelled cycle automatically or via command from
the host processor. For the R2 versions of the M-986,
A-law is used for coding/decoding. The M-986 is con-
figured and controlled through an integral coprocessor
port.
Ordering Information
Part #
M-986-1R2P
M-986-1R2PL
M-986-2R2P
M-986-2R2PL
Description
40-pin plastic DIP, Single Channel
44-pin PLCC, Single Channel
40-pin plastic DIP, Dual Channel
44-pin PLCC, Dual Channel
DS-M976-2R2-R3
www.clare.com
1




M-986-1R2P pdf, 반도체, 판매, 대치품
M-986-2R2
The R2B transceiver detects the signal, enters STATE
2, and outputs the received tone code to its host via the
coprocessor port. If the R2B host had determined the
next tone to transmit and written a transmit command
to the transceiver prior to entry into STATE 2, the state
transition will cause this tone to be transmitted.
Otherwise, the R2B transmitter waits for a transmit
tone command from the host, and starts transmitting a
tone once the transmit tone command is received.
The R2F transceiver detects the backward signal,
enters STATE 2, and outputs the received tone code to
its host. Entry into STATE 2 unconditionally disables
the transmitter.
The R2B transceiver detects the absence of signal,
enters STATE 1, and informs the host with the end-of-
tone code if configured to do so. Entry into STATE 1
unconditionally disables the transmitter.
The R2F transceiver detects the absence of signal,
enters STATE 1, and informs the host with the end-of-
tone code if configured to do so. If the R2F host had
determined the next signal to transmit and written a
transmit command to the transceiver prior to entry into
STATE 1, the state transition will cause this signal to be
transmitted. Otherwise, the transmitter remains silent
until the next transmit command by its host.
Forward/Backward Frequencies (FB): When forward
mode is selected, the R2F (forward) frequencies are
transmitted and R2B (backward) frequencies are
received. When backward mode is selected, R2B fre-
quencies are transmitted and R2F frequencies are
received. The R2F frequencies are 1380, 1500, 1620,
1740, 1860, and 1980 Hertz. The R2B frequencies are
540, 660, 780, 900, 1020, and 1140 Hz.
Initial Configuration: The configuration of the M-986
immediately after a reset will be as follows:
· End-of-digit indication ON
· Forward mode ON
· Channel disabled
· 2-of-6 input/output
· External serial and serial frame clocks.
Also, the M-986 will place 00 hex on the coprocessor
port to indicate to the host processor that it is working.
Transmit Tone Command
The transmit tone command allows the host processor
to transmit any two of the 6 possible frequencies in the
transmission mode the channel has been configured
for (forward or backward). The format of the command
depends on whether the M-986 is configured for bina-
ry format or 2-of-6 format.
Recieved Tone Detection
When a tone is detected by the M-986, the TBLF out-
put goes low, indicating reception of the tone to the
host processor. The host processor can determine
which tone was detected and which channel the tone
was detected on by reading data from the M-986
coprocessor port. The M-986 will return a single byte
indicating the tone received and the channel that the
tone was received on.The format of the returned byte
depends on whether the M-986 is configured for bina-
ry or 2-of-6 coding.
Coprocessor Port
Commands are written to the M-986 via the coproces-
sor port, and data indicating the received R2 MF tone
is read from the coprocessor port.
Writing to the Coprocessor Port: The following
sequence describes writing a command to the M-986.
(1) The WR signal is driven low by the host processor.
(2) The RBLE (receive buffer latch empty) signal tran-
sitions to a logic high level.
(3) Data is written from LD7-LD0 to the receive buffer
latch (D7-D0) when the WR signal goes high.
(4) The RBLE signal transitions to a logic low level after
the M-986 reads the data. This signals the host
processor that the receive buffer is empty.
Note: The RBLE should be low before writing to the
coprocessor.
Reading the Coprocessor Port: The following
sequence describes reading received tone information
from the coprocessor port.
(1) The TBLF (transmit buffer latch full) port pin on the
M-986 goes low indicating the reception of a tone.
(2) The host processor detects the low logic level on
the TBLF pin either by polling a connected port pin or
by an interrupt.
(3) The host processor drives the RD signal low.
(4) The TBLF (transmit buffer latch full) signal transi-
tions to a logic high level.
(5) Data is driven onto LD7-LD0 by the M-986 until the
RD signal is driven high by the host processor.
Clock Characeristics and Timing
Internal Clock Option: The internal oscillator is enabled
by connecting a crystal across X1 and X2/CLKIN. The
crystal must be 20.48 MHz, fundamental mode, and
parallel resonant, with an effective series resistance of
30 ohms, a power dissipation of 1 mW, and bespeci-
fied at a load capacitance of 20 pf.
4
www.clare.com
Rev. 3

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M-986-1R2P 전자부품, 판매, 대치품
Electrical Characteristics/Temperature Range
Parameter
Test Conditions
ICC Supply current f = 20.5 MHz, VCC = 5.5V, - 50
TA = 0˚ to 70 ˚C
VOH High-level output voltage
IOH = MAX
IOH = 20 µ A
VOL Low-level output voltage
IOL = MAX
IOZ Off-state output current
VCC = MAX
VO = 2.4 V
VO = 0.4 V
II Input current
VI = VSS to VCC Except CLKIN
CLKIN
CI Input capacitance Data bus
All others
f = 1 MHz, all other pins 0 V
CO Output capacitance Data bus
All others
External Frequency Specifications
tC(MC)
tr(MC)
tf(MC)
Parameter
Master clock cycle time
Rise time master clock input
Pulse duration master clock
Recommended Operating Conditions
Parameter
VCC Supply voltage
VSS Supply voltage
VIH High-level input voltage
VIL Low-level input voltage
IOH High-level output current (all outputs)
IOL Low-level output current (all outputs)
All inputs except CLKIN
CLKIN
MC/PM
All inputs except MC/MP
MC/MP
Coprocessor Interface Timing
td(R-A)
td(W-A)
ta(RD)
th(RD)
tsu(WR)
th(WR)
tw(RDL)
tw(WRL)
twr(RBLE)
Parameter
RD low to TBLF high
WR low to RBLE high
RD low to data valid
Data hold time after RD high
Data setup time prior to WR high
Data hold time after WR high
RD low-pulse duration
WR low-pulse duration
RBLEto RBLE
Rev. 3 www.clare.com
M-986-2R2
Min
75
2.4
VCC -0.4
-
-
-
-
-
-
-
-
-
Typ
mA
3
-
0.3
-
-
-
-
25
15
25
10
Max Unit
-V
-V
0.6 V
20 µA
-20 µA
±20 µA
±50 µA
- pF
- pF
- pF
- pF
Min
48.818
-
20
Nom
48.828
5
-
Max
48.838
10
-
Unit
ns
ns
ns
Min
Nom
Max Unit
4.75 5 5.25 V
- 0 -V
2 - -V
3 - -V
2.2 - - V
- - 0.8 V
- - 0.6 V
- - -300 µA
- - 2 mA
Min
Nom
Max Unit
- - 75 ns
- - 75 ns
- - 80 ns
25 -
- ns
30 -
- ns
25 -
- ns
80 -
- ns
60 -
- ns
- - 1 ms
7

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관련 데이터시트

부품번호상세설명 및 기능제조사
M-986-1R2P

MFC Transceivers

Clare  Inc.
Clare Inc.
M-986-1R2PL

MFC Transceivers

Clare  Inc.
Clare Inc.

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