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부품번호 M2081 기능
기능 VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
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M2081 데이터시트, 핀배열, 회로
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n M2080/81/82
M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M2080/81/82 and M2085/86/87 are VCSO (Voltage
Controlled SAW Oscillator) based
clock PLLs designed for FEC clock
ratio translation in 10Gb optical
systems such as OC-192 or 10GbE.
They support FEC (Forward Error
Correction) clock multiplication
ratios, both forward (mapping) and
inverse (de-mapping). Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
Integrated SAW delay line; Output of 15 to 700 MHz *
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
LVPECL clock output (CML and LVDS options available)
Pin-selectable PLL divider ratios support FEC ratios
• M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping
• M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping
• M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
Options for Hitless Switching (HS) with or without
Phase Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
FIN_SEL0
FEC_SEL0
FEC_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
28 18
29 17
30 M 2 0 8 0
31
32 S e r i e s
16
15
14
33 13
34 ( T o p V i e w ) 12
35 11
36 10
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M2081-11-622.0800 FEC De-Map Ratios
FEC De-Map
PLL Ratio
Mfec / Rfec
Base Input Rate 1
(MHz)
Output Clock
(either output)
MHz
1/1
237/255
238/255
622.0800
666.5143
669.3266
622.08
or
155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown
divided by “Mfin” (as shown in Tables 3 and 4 on pg. 3).
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
NBW
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_ACK
REF_SEL
AUTO
M2080 Series
MUX
0 Rfec
Div
1
PLL
Phase
Detector
0
1
Auto
Ref Sel
LOL Phase
Detector
Mfec Div
2
FEC_SEL1:0
2
FIN_SEL1:0
3
P_SEL2:0
Mfec / Rfec Divider
LUT
Mfin Divider
LUT
Loop Filter
Mfin Divider
(1, 4, 8, 32 or
1, 4, 8, 16)
VCSO
P Divider
(1, 4, 8, 32 or TriState)
Tri-state
P Divider
LUT
Figure 2: Simplified Block Diagram
LOL
FOUT
nFOUT
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
Revised 30Jul2004
M2080/81/82 VCSO FEC PLL with AutoSwitch for SONET/OTN
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400




M2081 pdf, 반도체, 판매, 대치품
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Preliminary Information
M2082/87: FEC De-map LUT, Both OTU1 and OTU2
Use this option for both OTU1 or OTU2 de-mapping
applications. The Mfec divider value is kept nearly
constant to maintain similar loop bandwidth using one
set of external filter component values.
FEC_SEL1:0
10
Mfec
Rfec
Description
Base Input
Rate (MHz)
Fvcso =
Base Output
Rate (MHz)
For M2082 or M2087 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
0 0 79 85 237/255 OTU2 to OC-192 decode 669.3266 622.08
0 1 79 79 OC-192 repeater or jitter attenuator 622.08 622.08
1 0 84 90 238/255 OTU1 to OC-48 decode 666.5143 622.08
1 1 84 84 OC-48 repeater or jitter attenuator 622.08 622.08
Table 7: M2082/87: FEC De-map LUT, Both OTU1 and OTU2
P Divider Look-Up Table (LUT)
The P_SEL2:0 pins select the P divider values, which set
the output clock frequency. A P divider of value of 1 will
provide a 622.08MHz output when using a 622.08MHz
VCSO, for example. P divider values of 4, 8, or 32 are
also available, plus a TriState mode. The output can be
placed into the valid states as listed in Table 8.
P_SEL2:0
P Value
M2080-622.0800 or M2085-622.0800
Output Frequency (MHz)
000
001
010
011
100
101
110
111
32 19.44
32 19.44
1 622.08
4 155.52
8 77.76
4 155.52
8 77.76
TriState
N/A
Table 8: P Divider Look-Up Table (LUT)
General Guidelines for Phase Detector Frequency
The phase detector frequency (Fpd) is equal to the
input reference frequency (Fref) divided by the Rfec
divider value, or:
Fpd = Fref / Rfec
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz.
When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive. The LOL pin
should not be used during loop timing mode.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the LOL
output for clock fault detection.
FUNCTIONAL DESCRIPTION
The M208x Series is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance and establishes the output
frequency of the VCSO (Voltage Controlled SAW
Oscillator). In a given M208x Series device, the VCSO
center frequency is fixed. A common center frequency
is 622.08MHz, for SONET or SDH optical network
applications. The VCSO center frequency is specified at
time of order (see “Ordering Information” on pg. 14).
The VCSO has a guaranteed tuning range of ±120 ppm
(commercial temperature grade).
Pin selectable dividers are used within the PLL and
for the output clock. This enables tailoring of device
functionality and performance. The FEC feedback and
reference dividers (the “Mfec Divider” and “Rfec
Divider”) provide the multiplication ratios necessary to
accomodate clock translation for both forward and
inverse Forward Error Correction. The Mfec and Rfec
dividers also control the phase detector frequency. The
feedback divider (labeled “Mfin Divider”) provides the
broader division options needed to accomodate various
reference clock frequencies.
For example, the M2082-11-622.0800 (see “Ordering
Information” on pg. 14) has a 622.08MHz VCSO
frequency:
The FEC de-mapper PLL ratios (in Tables 6 and 7)
enable the M2082-11-622.0800 to accept “base” input
reference frequencies of: 666.5143 (OTU1), 669.3266
(OTU2), and 622.08MHz (OC-192).
The Mfin feedback divider enables the actual input
reference clock to be the base input frequency
divided by 1, 4, 8, or 32 or 16. Therefore, for the base
input frequency of 622.08MHz, the actual input
reference clock frequencies can be: 622.08, 155.52,
77.76, and 19.44 or 38.88MHz. (See Tables 3 and 4 on
pg. 3.)
Key to Device Variants and Look-up Table Options
Device
Look-up Table Option
Variant Mfin Lookup Table is: Mfec Look-up Table is:
M2080
M2081
Table 3
Table 5 (FEC mapper LUT)
(includes divider value 32) Table 6 (FEC de-mapper LUT)
M2082
Table 7 (FEC de-mapper LUT)
M2085
M2086
Table 4
Table 5 (FEC mapper LUT)
(includes divider value 16) Table 6 (FEC de-mapper LUT)
M2087
Table 7 (FEC de-mapper LUT)
Table 9: Key to Device Variants and Look-up Table Options
The P divider scales the VCSO output enabling lower
output frequency selections (Table 8).
M2080/81/82 M2085/86/87 Datasheet Rev 0.4
4 of 14
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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M2081 전자부품, 판매, 대치품
Integrated
Circuit
Systems, Inc.
M2080/81/82, M2085/86/87
VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN
Preliminary Information
AutoSwitch (AUTO) Reference Clock Reselection
This device offers an automatic reference clock
reselection feature for switching input reference clocks
upon a reference clock failure. With the AUTO input pin
set to high and the LOL output low, the device is placed
into automatic reselection (AutoSwitch) mode. Once in
AutoSwitch mode, when LOL then goes high (due to a
reference clock fault), the input clock reference is
automatically reselected internally, as indicated by the
state change of the REF_ACK output. Automatic clock
reselection is made only once (it is non-revertive).
Re-arming of automatic mode requires placing the
device into manual selection (Manual Select) mode
(AUTO pin low) before returning to AutoSwitch mode
(AUTO pin high).
Using the AutoSwitch Feature
See also Table 10, Example AutoSwitch Sequence.
In application, the system is powered up with the device
in Manual Select mode (AUTO pin is set low), allowing
sufficient time for the reference clock and device PLL to
settle. The REF_SEL input selects the reference clock to
be used in Manual Select mode and the initial reference
clock used in AutoSwitch mode. The REF_SEL input state
must be maintained when switching to AutoSwitch
mode (AUTO pin high) and must still be maintained until a
reference fault occurs.
Once a reference fault occurs, the LOL output goes high
and the input reference is automatically reselected. The
REF_ACK output always indicates the reference selection
status and the LOL output always indicates the PLL lock
status.
A successful automatic reselection is indicated by a
change of state of the REF_ACK output and a momentary
level high of the LOL output (minimum high time is 10
ns).
If an automatic reselection is made to a non-valid
reference clock (one to which the PLL cannot lock),
the REF_ACK output will change state but the LOL
output will remain high.
No further automatic reselection is made; only one
reselection is made each time the AutoSwitch mode is
armed. AutoSwitch mode is re-armed by placing the
device into Manual Select mode (AUTO pin low) and then
into AutoSwitch mode again (AUTO pin high).
Following an automatic reselection and prior to
selecting Manual Select mode (AUTO pin low), the
REF_SEL pin has no control of reference selection.
To prevent an unintential reference reselection,
AutoSwitch mode must not be re-enabled until the
desired state of the REF_SEL pin is set and the LOL output
is low. It is recommended to delay the re-arming of
AutoSwitch mode, following an automatic reselection, to
ensure the PLL is fully locked on the new reference. In
most system configurations, where loop bandwidth is in
the range of 100-1000 Hz and damping factor below 10,
a delay of 500 ms should be sufficient. Until the PLL is
fully locked intermittent LOL pulses may occur.
Example AutoSwitch Sequence
0 = Low; 1 = High. Example with REF_SEL initially set to 0 (i.e., DIF_REF0 selected)
REF_SEL Selected REF_ACK AUTO LOL Conditions
Input Clock Input Output Input Output
Initialization
0 DIF_REF0 0
0 1 Device power-up. Manual Select mode. DIF_REF0 input selected reference, not yet locked to.
0 DIF_REF0 0
0 -0- LOL to 0: Device locked to reference (may get intermittent LOL pulses until fully locked).
0 DIF_REF0 0 -1- 0 AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as initial reference clock).
Operation & Activation
0 DIF_REF0 0
1 0 Normal operation with AutoSwitch mode armed, with DIF_REF0 as initial reference clock.
0 DIF_REF0 0
0 -DIF_REF1- -1-
0 DIF_REF1 1
1 -1- LOL to 1: Clock fault on DIF_REF0, loss of lock indicated by LOL pin, ...
1 1 ... and immediate automatic reselection to DIF_REF1 (indicated by REF_ACK pin).
1 -0- LOL to 0: Device locks to DIF_REF1 (assuming valid clock on DIF_REF1).
-1- DIF_REF1 1
Re-initialization
1 0 REF_SEL set to 1: Prepares for Manual Selection of DIF_REF1 before then re-arming AutoSwitch.
1 DIF_REF1 1 -0- 0 AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as reference.
1 DIF_REF1 1
-1- 0 AUTO set to 1: Device is placed in AutoSwitch mode (delay recommended to ensure device fully
locked), re-initializing AutoSwitch with DIF_REF1 now specified as the initial reference clock.
Table 10: Example AutoSwitch Sequence
M2080/81/82 Datasheet Rev 0.4
7 of 14
Revised 30Jul2004
Integrated Circuit Systems, Inc. Networking & Communications www.icst.com tel (508) 852-5400

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