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PDF FIN1019 Data sheet ( Hoja de datos )
| Número de pieza | FIN1019 | |
| Descripción | 3.3V LVDS High Speed Differential Driver/Receiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de FIN1019 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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April 2001
Revised September 2001
FIN1019
3.3V LVDS High Speed Differential Driver/Receiver
General Description
This driver and receiver pair are designed for high speed
interconnects utilizing Low Voltage Differential Signaling
(LVDS) technology. The driver translates LVTTL signals to
LVDS levels with a typical differential output swing of
350mV and the receiver translates LVDS signals, with a
typical differential input threshold of 100mV, into LVTTL
levels. LVDS technology provides low EMI at ultra low
power dissipation even at high frequencies. This device is
ideal for high speed clock or data transfer.
Features
s Greater than 400Mbs data rate
s 3.3V power supply operation
s 0.5ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s 100mV receiver input sensitivity
s Fail safe protection open-circuit, shorted and terminated
conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Flow-through pinout simplifies PCB layout
s 14-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number Package Number
Package Description
FIN1019M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1019MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Function Table
Connection Diagram
Inputs
Outputs
RIN+
L
RIN−
H
RE
L
ROUT
L
H LL
H
X XH
Z
Fail Safe Condition
L
H
DIN
DE
DOUT+
DOUT−
L H LH
H H HL
X L ZZ
Open−Circuit or Z
H
LH
H = HIGH Logic Level
Z = High Impedance
L = LOW Logic Level
X = Don’t Care
Fail Safe = Open, Shorted, Terminated
Pin Descriptions
Pin Name
DIN
DOUT+
DOUT−
DE
RIN+
RIN−
ROUT
RE
VCC
GND
NC
Description
LVTTL Data Input
Non-inverting LVDS Output
Inverting LVDS Output
Driver Enable (LVTTL, Active HIGH)
Non-Inverting LVDS Input
Inverting LVDS Input
LVTTL Receiver Output
Receiver Enable (LVTTL, Active LOW)
Power Supply
Ground
No Connect
© 2001 Fairchild Semiconductor Corporation DS500506
www.fairchildsemi.com
1 page  
Note A: Input pulses have frequency = 10 MHz, tR or tF = 1ns
Note B: CL includes all probe and fixture capacitance
FIGURE 6. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit
TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Applied Voltages (V)
VIA
1.25
1.15
2.4
2.3
0.1
0
1.5
0.9
2.4
1.8
0.6
0
VIB
1.15
1.25
2.3
2.4
0
0.1
0.9
1.5
1.8
2.4
0
0.6
Resulting Differential
Input Voltage (mV)
VID
100
−100
100
−100
100
−100
600
−600
600
−600
600
−600
Resulting Common Mode
Input Voltage (V)
VIC
1.2
1.2
2.35
2.35
0.05
0.05
1.2
1.2
2.1
2.1
0.3
0.3
5 www.fairchildsemi.com
5 Page 
DC / AC Typical Performance Curves (Continued)
FIGURE 30. Differential Propagation Delay vs.
Power Supply Voltage
FIGURE 31. Differential Propagation Delay vs.
Ambient Temperature
FIGURE 32. Differential Skew (tPHL - tPHL) vs.
Power Supply Voltage
FIGURE 33. Differential Skew (tPLH - tPHL) vs.
Ambient Temperature
FIGURE 34. Differential Propagation Delay vs.
Differential Input Voltage
FIGURE 35. Differential Propagation Delay vs.
Common-Mode Voltage
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet FIN1019.PDF ] | |
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