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PDF FIN1048 Data sheet ( Hoja de datos )

Número de pieza FIN1048
Descripción 3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FIN1048 Hoja de datos, Descripción, Manual

September 2001
Revised August 2003
FIN1048
3.3V LVDS 4-Bit Flow-Through
High Speed Differential Receiver
General Description
This quad receiver is designed for high speed interconnect
utilizing Low Voltage Differential Signaling (LVDS) technol-
ogy. The receiver translates LVDS levels, with a typical dif-
ferential input threshold of 100mV, to LVTTL signal levels.
LVDS provides low EMI at ultra low power dissipation even
at high frequencies. This device is ideal for high speed
transfer of clock and data.
The FIN1048 can be paired with its companion driver, the
FIN1047, or any other LVDS driver.
Features
s Greater than 400Mbs data rate
s Flow-through pinout simplifies PCB layout
s 3.3V power supply operation
s 0.4ns maximum differential pulse skew
s 2.5ns maximum propagation delay
s Low power dissipation
s Power-Off protection
s Fail safe protection for open-circuit, shorted and termi-
nated conditions
s Meets or exceeds the TIA/EIA-644 LVDS standard
s Pin compatible with equivalent RS-422 and LVPECL
devices
s 16-Lead SOIC and TSSOP packages save space
Ordering Code:
Order Number Package Number
Package Description
FIN1048M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
FIN1048MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Description
ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs
RIN1+, RIN2+, RIN3+, RIN4+ Non-Inverting LVDS Inputs
RIN1, RIN2, RIN3, RIN4Inverting LVDS Inputs
EN Driver Enable Pin
EN
VCC
GND
Inverting Driver Enable Pin
Power Supply
Ground
Function Table
Inputs
Outputs
EN
EN
RIN+
ROUT
ROUT
H L or Open H
L
H
H L or Open L
H
L
H L or Open Fail Safe Condition H
X
HX X
Z
L or Open
X
X
X
Z
H = HIGH Logic Level L = LOW Logic Level X = Don’t Care
Z = High Impedance
Fail Safe = Open, Shorted, Terminated
© 2003 Fairchild Semiconductor Corporation DS500588
www.fairchildsemi.com

1 page




FIN1048 pdf
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
5 www.fairchildsemi.com

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