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What is FM24C05U?

This electronic component, produced by the manufacturer "Fairchild Semiconductor", performs the same function as "4K-Bit Standard 2-Wire Bus Interface Serial EEPROM".


FM24C05U Datasheet PDF - Fairchild Semiconductor

Part Number FM24C05U
Description 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
Manufacturers Fairchild Semiconductor 
Logo Fairchild Semiconductor Logo 


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August 2000
FM24C04U/05U – 4K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
The FM24C04U/05U devices are 4096 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol. They are designed to
minimize device pin count and simplify PC board layout require-
ments.
The upper half (upper 2Kbit) of the memory of the FM24C05U can
be write protected by connecting the WP pin to VCC. This section of
memory then becomes unalterable unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the FM24C32 or FM24C65 datasheets for more informa-
tion.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
Features
I Extended operating voltage 2.7V – 5.5V
I 400 KHz clock frequency (F) at 2.7V - 5.5V
I 200µA active current typical
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I IIC compatible interface
– Provides bi-directional data transfer protocol
I Sixteen byte page write mode
– Minimizes total write time per byte
I Self timed write cycle
Typical write cycle time of 6ms
I Hardware Write Protect for upper half (FM24C05U only)
I Endurance: 1,000,000 data changes
I Data retention greater than 40 years
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
SDA
SCL
A2
A1
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
WORD
ADDRESS
COUNTER
R/W
XDEC
H.V. GENERATION
TIMING &CONTROL
E2PROM
ARRAY
YDEC
CK
DIN
DATA REGISTER
DOUT
© 2000 Fairchild Semiconductor International
FM24C04U/05U Rev. A.3
1
www.fairchildsemi.com

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FM24C05U equivalent
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
VCC x 0.1 to VCC x 0.9
10 ns
Input & Output Timing Levels VCC x 0.3 to VCC x 0.7
Output Load
1 TTL Gate and CL = 100 pF
AC Testing Input/Output Waveforms
0.9VCC
0.1VCC
0.7VCC
0.3VCC
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 KHz
Min Max
400 KHz
Min Max
fSCL SCL Clock Frequency
TI Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
100
400
50
tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9
tBUF Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
tHD:STA
tLOW
tHIGH
tSU:STA
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tDH
tWR
(Note 4)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
4.5V to 5.5V VCC
2.7V to 4.5V VCC
00
250 100
1 0.3
300 300
4.7 0.6
300 50
10 10
15 15
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C04U/05U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.
Bus Timing
tF
tLOW
SCL
SDA
tSU:STA
tHD:STA
;;IN
SDA
OUT
tAA
tHIGH
tHD:DAT
tR
tLOW
tSU:DAT
tDH
tSU:STO
tBUF
FM24C04U/05U Rev. A.3
5
www.fairchildsemi.com


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Featured Datasheets

Part NumberDescriptionMFRS
FM24C05UThe function is 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM. Fairchild SemiconductorFairchild Semiconductor

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