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부품번호 | FM24C256FLZYYX 기능 |
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기능 | 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
June 2000
FM24C256
256 KBit 2-Wire Bus Interface
Serial EEPROM with Write Protect
General Description
The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS
nonvolatile electrically erasable memory. These devices offer the
designer different low voltage and low power options. They
conform to all requirements in the Extended IIC 2-wire protocol.
Furthermore, they are designed to minimize device pin count and
simplify PC board layout requirements.
The entire memory array can be write disabled (Write Protection)
by connecting the WP pin to VCC.
Functional address lines allow up to eight devices on the same
bus, for up to a total of 2 Mbit address space.
The IIC communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability, and low power con-
sumption.
Features
I Extended Operating Voltages
— C256: 4.5V - 5.5V
— C256L: 2.7V - 5.5V
— C256LZ: 2.7V - 5.5V
I Low Power CMOS
— 1mA active current typical
— C256/C256L: 10µA standby current typical
— C256LZ: less than 1µA standby current
I 2-wire IIC serial interface
I 64 byte page write mode
I Max write cycle time of 6ms byte/page
I 40 years data retention
I Endurance: 100,000 data changes
I Hardware write protect for entire array
I Schmitt trigger inputs for noise suppression
I Electrostatic discharge protection > 4000V
I 8-pin DIP and 8-pin SO (150 mil) packages. Contact factory
for CSP package availability
Block Diagram
VCC
WP
SDA
SCL
A2
A1
A0
WRITE
LOCKOUT
START
STOP
LOGIC
START CYCLE
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
LOAD
INC
WORD
ADDRESS
COUNTER
XDEC
R/W
H.V. GENERATION
TIMING &CONTROL
E2PROM
ARRAY
YDEC
CK
DIN
DATA REGISTER
DOUT
DS800023-1
© 2000 Fairchild Semiconductor International
FM24C256 rev. B.3
1
www.fairchildsemi.com
Absolute Maximum Ratings
Operating Conditions
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 seconds)
ESD Rating
–65°C to +150°C
6.5V to –0.3V
+300°C
4000V min.
Ambient Operating Temperature
FM24C256/L/LZ
FM24C256F/FL/FLZ
FM24C256E/LE/LZE
FM24C256FE/FLE/FLZE
Positive Power Supply
FM24C256/E
FM24C256F/FE
FM24C256L/LZ
FM24C256FL/FLZ
FM24C256LE/LZE
FM24C256FLE/FLZE
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Limits
Typ
ICCA
Active Power Supply Current
fSCL = 100 kHz
fSCL = 400 kHz
ISB Standby Current
VIN = GND or VCC
ILI Input Leakage Current
VIN = GND to VCC
ILO Output Leakage Current
VOUT = GND to VCC
VIL Input Low Voltage
–0.3
VIH Input High Voltage
VCC x 0.7
VOL Output Low Voltage
IOL = 2.1 mA
0.5
10
0.1
0.1
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
4.5V to 5.5V
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 5.5V
2.7V to 4.5V
Max
1.0
Units
mA
50
1
1
VCC x 0.3
VCC + 0.5
0.4
µA
µA
µA
V
V
V
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
ICCA Active Power Supply Current
ISB
(Note 1)
Standby Current for L
Standby Current for LZ
ILI Input Leakage Current
ILO Output Leakage Current
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
fSCL = 100 kHz
fSCL = 400 kHz
VIN = GND or VCC = 4.5V - 5.5V
VIN = GND or VCC = 2.7V - 4.5V
VIN = GND or VCC = 4.5V - 5.5V
VIN = GND or VCC = 2.7V - 4.5V
VIN = GND to VCC
VOUT = GND to VCC
–0.3
IOL = 2.1 mA
VCC x 0.7
Limits
Typ
0.5
10
1
10
0.1
0.1
0.1
Max
1.0
Units
mA
50
10
50
1
1
1
VCC x 0.3
VCC + 0.5
0.4
µA
µA
µA
V
V
V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V
Symbol
Test
Conditions
CI/O Input/Output Capacitance (SDA)
VI/O = 0V
CIN
Input Capacitance (A0, A1, A2, SCL)
VIN = 0V
Max
8
6
Units
pF
pF
Note 1: Typical values are for TA = 25°C and nominal supply voltage (5V).
FM24C256 rev. B.3
4 www.fairchildsemi.com
4페이지 Write Cycle Timing
ACKNOWLEDGE
ACK (acknowledge) is a software convention used to indicate
successful data transfers. The transmitting device, either master or
slave, will release the bus after transmitting eight bits. During the ninth
clock cycle the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
The FM24C256xxx device will always respond with an acknowl-
edge after recognition of a start condition and its slave address. If
Write Cycle Timing:
both the device and a WRITE operation have been selected, the
FM24C256xxx will respond with an acknowledge after the receipt
of each subsequent eight bit word.
In the READ mode the FM24C256xxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an acknowl-
edge. If an acknowledge is detected and no stop condition is
generated by the master, the slave will continue to transmit data.
If an acknowledge is not detected, the slave will terminate further
data transmissions and await the stop condition to return to the
standby power mode.
SCL
SDA
8th BIT
WORD n
ACK
Data Validity (Figure 1)
tWR
STOP
START
CONDITION
CONDITION
DS800023-4
SCL DATA STABLE DATA
CHANGE
SDA
Definition of Start and Stop (Figure 2)
SCL
SDA
START CONDITION
Acknowledge Response from Receiver (Figure 3)
SCL FROM
MASTER
1
Data Output
from Transmitter
Data Output
from Receiver
START
FM24C256 rev. B.3
7
DS800023-5
STOP CONDITION
89
DS800023-6
ACKNOWLEDGE
DS800023-7
www.fairchildsemi.com
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
FM24C256FLZYYX | 256 KBit 2-Wire Bus Interface Serial EEPROM with Write Protect | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |