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PDF FM24C64LZ Data sheet ( Hoja de datos )
| Número de pieza | FM24C64LZ | |
| Descripción | 64K-Bit Standard 2-Wire Bus Interface Serial EEPROM | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FM24C64 – 64K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
December 2001
General Description
FM24C64 is a 64Kbit CMOS non-volatile serial EEPROM orga-
nized as 8K x 8 bit memory. This device confirms to Extended IIC
2-wire protocol that allows accessing of memory in excess of
16Kbit on an IIC bus. This serial communication protocol uses a
Clock signal (SCL) and a Data signal (SDA) to synchronously
clock data between a master (e.g. a microcontroller) and a slave
(EEPROM). FM24C64 is designed to minimize pin count and
simplify PC board layout requirements.
FM24C64 offers hardware write protection where by the entire
memory array can be write protected by connecting WP pin to VCC.
This section of memory then becomes unalterable until the WP pin
is switched to VSS.
“LZ” and “L” versions of FM24C64 offer very low standby current
making them suitable for low power applications. This device is
offered in SO, TSSOP and DIP packages.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Features
I Extended operating voltage: 2.5V to 5.5V
I Up to 400 KHz clock frequency at 2.5V to 5.5V
I Low power consumption
— 0.5mA active current typical
— 10µA standby current typical
— 1µA standby current typical (L version)
— 0.1µA standby current typical (LZ version)
I Schmitt trigger inputs
I 32 byte page write mode
I Self timed write cycle (6ms typical)
I Hardware Write Protection for the entire array
I Endurance: up to 100K data changes
I Data Retention: Greater than 40 years
I Packages: 8-Pin DIP, 8-Pin SO and 8-Pin TSSOP
I Temperature range
— Commercial: 0°C to +70°C
— Industrial (E): -40°C to +85°C
— Automotive (V): -40°C to +125°C
Block Diagram
VSS
VCC
WP
SDA
SCL
A2
A1
A0
WRITE
LOCKOUT
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
WORD
ADDRESS
COUNTER
R/W
DIN
H.V. GENERATION
TIMING &CONTROL
XDEC
E2PROM
ARRAY
YDEC
CK
DATA REGISTER
DOUT
© 2001 Fairchild Semiconductor Corporation
FM24C64 Rev. C
1
www.fairchildsemi.com
1 page  
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
VCC x 0.1 to VCC x 0.9
10 ns
Input & Output Timing Levels VCC x 0.3 to VCC x 0.7
Output Load
1 TTL Gate and CL = 100 pF
AC Testing Input/Output Waveforms
0.9VCC
0.1VCC
0.7VCC
0.3VCC
Read and Write Cycle Limits (Standard and Low VCC Range 2.5V - 5.5V)
Symbol
Parameter
100 KHz
Min Max
400 KHz
Min Max
fSCL SCL Clock Frequency
TI Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
100
400
50
tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9
tBUF Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.3
tHD:STA
tLOW
tHIGH
tSU:STA
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tDH
tWR
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
00
250 120
1 0.3
300 300
4.7 0.6
100 50
66
Units
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle,
the FM24C64 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave
address. Refer "Write Cycle Timing" diagram.
Bus Timing
SCL
SDA
IN
tSU:STA
SDA
OUT
tF
tLOW
tHD:STA
tHIGH
tR
tLOW
tHD:DAT
tSU:DAT
tAA tDH
tSU:STO
tBUF
FM24C64 Rev. C
5 www.fairchildsemi.com
5 Page 
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.
Current Address Read
Internally the FM24C64 contains an address counter that main-
tains the address of the last byte accessed, incremented by one.
Therefore, if the last access (either a read or write) was to address
n, the next read operation would access data from address n + 1.
Upon receipt of the slave address with R/W set to "1," the
FM24C64 issues an acknowledge and transmits the eight bit
word. The master will not acknowledge the transfer but does
generate a stop condition, and therefore the FM24C64 discontin-
ues transmission. Refer Figure 6 for the sequence of address,
acknowledge and data transfer.
Random Read
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to "1," the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address with the R/W bit set to "0" and then the byte
address. After the byte address acknowledge, the master imme-
diately issues another start condition and the slave address with
the R/W bit set to one. This will be followed by an acknowledge
from the FM24C64 and then by the eight bit word. The master will
not acknowledge the transfer but does generate the stop condi-
tion, and therefore the FM24C64 discontinues transmission.
Refer Figure 7 for the address, acknowledge, and data transfer
sequence.
Sequential Read
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The FM24C64 continues to output data for each acknowl-
edge received. The read operation is terminated by the master not
responding with an acknowledge or by generating a stop condi-
tion.
The data output is sequential with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" to the
beginning of the memory. FM24C64 continues to output data for
each acknowledge received. Refer Figure 8 for the address,
acknowledge, and data transfer sequence.
Current Address Read (Figure 6)
Bus Activity:
Master
S
T
A SLAVE
R ADDRESS
T
SDA Line
101 0
1
Bus Activity:
EEPROM
A
C
K
DATA
Random Read (Figure 7)
S
T
Bus Activity:
A
R
Master T
SLAVE
ADDRESS
WORD
ADDRESS (1)
WORD
ADDRESS (0)
S
T
A
R
T
SDA Line
Bus Activity:
EEPROM
0
AAA
CCC
KKK
S
T
O
P
NO
A
C
K
SLAVE
ADDRESS
1
A
C
K
DATA
S
T
O
P
NO
A
C
K
Sequential Read (Figure 8)
Bus Activity:
Master
Slave
Address
SDA Line
Bus Activity:
EEPROM
A
C DATA n +1
K
A AA
C CC
K KK
DATA n +1
DATA n + 2
S
T
O
P
DATA n + x
NO
A
C
K
FM24C64 Rev. C
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FM24C64LZ.PDF ] | |
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