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FB2033 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 FB2033은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 FB2033 기능
기능 8-bit latched/registered/pass-thru Futurebus universal interface transceiver
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FB2033 데이터시트, 핀배열, 회로
Philips Semiconductors
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
Product specification
FB2033
FEATURES
8-bit transceivers
Latched, registered or straight through in either A to B or B to A
path
Drives heavily loaded backplanes with equivalent load
impedances down to 10.
High drive 100mA BTL Open Collector drivers on B-port
Allows incident wave switching in heavily loaded backplane buses
Reduced BTL voltage swing produces less noise and reduces
power consumption
Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
Compatible with IEEE Futurebus+ or proprietary BTL backplanes
Each BTL driver has a dedicated Bus GND for a signal return
Controlled output ramp and multiple GND pins minimize ground
bounce
Glitch-free power up/power down operation
Low ICC current
Tight output skew
Supports live insertion
QUICK REFERENCE DATA
SYMBOL
PARAMETER
tPLH Propagation delay
tPHL
AIn to Bn
tPLH Propagation delay
tPHL
Bn to AOn
COB Output capacitance (B0 – Bn only)
IOL Output current (B0 – Bn only)
AIn to Bn
ICC Supply current
(outputs Low or High)
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
TYPICAL
3.0
3.0
4.3
4.1
6
100
24
45
22
UNIT
ns
ns
pF
mA
mA
ORDERING INFORMATION
PACKAGES
52-pin Plastic Quad Flat Pack (QFP)
NOTE: Thermal mounting or forced air is recommended
PIN CONFIGURATION
COMMERCIAL RANGE
VCC = 5V±10%; Tamb = 0°C to +70°C
FB2033BB
DRAWING
NUMBER
SOT379-1
1995 May 25
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND 1
AO1 2
AI2 3
AO2 4
AI3 5
AO3 6
LOOPBACK 7
AI4 8
AO4 9
AI5 10
AO5 11
AI6 12
LOGIC GND 13
8-Bit Universal Transceiver
FB2033
52-lead PQFP
39 BUS GND
38 B1
37 BUS GND
36 B2
35 BUS GND
34 B3
33 BUS GND
32 B4
31 BUS GND
30 B5
29 BUS GND
28 B6
27 BUS GND
14 15 16 17 18 19 20 21 22 23 24 25 26
1
SG00068
853-1717 15279




FB2033 pdf, 반도체, 판매, 대치품
Philips Semiconductors
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
LOGIC DIAGRAM
OEB0 23
OEB1
SAB0
SAB1
LCAB
24
20
21
47
AIn 50
52,
2, 5,
8, 10,
12, 15
1 of 8 cells
D
En
D
Clk
LCBA 19
SBA0
SBA1
45
46
OEA 43
AOn 51
2, 4, 6, 9,
11, 14, 16
1 of 8 cells
Loopback 7
D
En
D
Clk
BGGnd 42
Product specification
FB2033
40 Bn
38,
36, 34,
32, 30,
28, 26
BGref
SG00069
1995 May 25
4

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FB2033 전자부품, 판매, 대치품
Philips Semiconductors
8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
Product specification
FB2033
LIVE INSERTION SPECIFICATIONS
SYMBOL
VBIASV Bias pin voltage
IBIASV Bias pin DC current
VBn
ILM
IHM
IBnPEAK
Bus voltage during pre-bias
Fall current during pre-bias
Rise current during pre-bias
Peak bus current during
insertion
IOLOFF Power up current
tGR Input glitch rejection
PARAMETER
VCC = 0 to 5.25V, Bn = 0 to 2.0V
VCC = 0 to 4.75V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
VCC = 4.5 to 5.5V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
B0 – B8 = 0V, Bias V = 5.0V
B0 – B8 = 2V, Bias V = 4.5 to 5.5V
B0 – B8 = 1V, Bias V = 4.5 to 5.5V
VCC = 0 to 5.25V, B0 – B8 = 0 to 2.0V,
Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns
VCC = 0 to 5.25V, OEB0 = 0.8V
VCC = 0 to 2.2V, OEB0 = 0 to 5V
VCC = 5.0V
LIMITS
MIN NOM
MAX
4.5 5.5
1
1.62
1
-1
1.0 1.35
10
2.1
10
100
100
UNIT
V
mA
µA
V
µA
µA
mA
µA
ns
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
A PORT LIMITS
Tamb = +25°C, VCC = 5V,
CL = 50pF, RL = 500
Tamb = 0 to 70°C,
VCC = 5V±10%,
CL = 50pF, RL = 500
MIN TYP MAX
MIN
MAX
UNIT
fMAX
Maximum clock frequency
Waveform 4
100 150
100
MHz
tPLH Propagation delay (thru mode)
tPHL
Bn to AOn
Waveform 1, 2
2.2 4.3 6.0
2.0 4.1 6.0
2.0
1.8
7.0
7.0
ns
tPLH Propagation delay (transparent latch)
tPHL
Bn to AOn
Waveform 1, 2
1.5 4.5 6.5
2.4 4.4 6.5
1.0
2.0
7.5
7.5
ns
tPLH Propagation delay
tPHL LCBA to AOn
Waveform 1, 2
2.0 3.8 5.5
2.2 4.3 6.0
1.8
1.7
6.0
6.5
ns
tPLH Propagation delay
tPHL SBAn to AOn
Waveform 1, 2
1.4 2.9 5.0
1.4 3.1 5.5
1.0
1.0
6.0
6.5
ns
tPLH Propagation delay (Loopback mode)
tPHL
AIn to AOn
Waveform 1, 2
2.0 3.8 6.0
2.0 3.9 6.0
2.8
2.3
7.0
7.0
ns
tPLH Propagation delay (Loopback mode)
tPHL Loopback to AOn
Waveform 1, 2
1.2 3.4 5.0
1.2 3.2 5.5
1.0
1.0
6.0
6.5
ns
tPZH Output enable time from High or Low
tPZL OEA to AOn
Waveform 5, 6
1.0 3.1 5.1
2.6 4.0 5.5
1.0
2.4
5.5
5.8
ns
tPHZ
tPLZ
Output disable time to High or Low
OEA to AOn
Waveform 5, 6
1.0 3.5 5.0
1.0 3.3 4.6
1.7
1.7
5.6
5.2
ns
tTLH
tTHL
tSK(o)
Output transition time, AOn Port
10% to 90%, 90% to 10%
Output to output skew, A port 1
Test Circuit and
Waveforms
Waveform 3
0.5 1.0
2.0
2.0
5.0
5.0
ns
1.5 ns
tSK(p)
Pulse skew 2
tPHL – tPLH MAX
Waveform 2
0.3 1.0
1.5 ns
NOTES:
1. Bn to AOn propagation delays are extended for 5 nanoseconds following B port excursions above 3.1 volts.
2. tPNactual – tPMactualfor any data input to output path compared to any other data input to output path where N and M are either LH or HL.
Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
3. tSK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 May 25
7

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