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부품번호 | FDC6303N 기능 |
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기능 | Digital FET/ Dual N-Channel | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 4 페이지수
August 1997
FDC6303N
Digital FET, Dual N-Channel
General Description
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. This device has been designed especially for
low voltage applications as a replacement for digital
transistors in load switching applications. Since bias
resistors are not required this one N-Channel FET can
replace several digital transistors with different bias
resistors like the IMHxA series.
Features
25 V, 0.68 A continuous, 2 A Peak.
RDS(ON) = 0.6 Ω @ VGS = 2.7 V
RDS(ON) = 0.45 Ω @ VGS= 4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors (IMHxA series)
with one DMOS FET.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
Mark: .303
SO-8
SOT-223
SOIC-16
43
52
61
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current
- Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG
ESD
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case
(Note 1)
© 1997 Fairchild Semiconductor Corporation
FDC6303N
25
8
0.68
2
0.9
0.7
-55 to 150
6.0
140
60
Units
V
V
A
W
°C
kV
°C/W
°C/W
FDC6303N Rev.C
Typical Electrical And Thermal Characteristics
5
ID = 0.5A
4
3
VDS = 5V
15V
10V
2
1
0
0 0.4 0.8 1.2 1.6 2
Qg , GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
150
100
50 Ciss
20
f = 1 MHz
10 VGS = 0V
Coss
Crss
5
0.1
0.5 1
2
5 10
25
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance Characteristics.
5
1
0.3
0.1
0.03
0.01
0.1
RDS(ON) LIMIT
VGS = 4.5V
SINGLE PULSE
R θJA = See note 1b
TA = 25°C
1m1s00µs
10ms
DC 1s100ms
0.2
0.5 1
2
5 10 20
VDS , DRAI N-SOURCE VOLTAGE (V)
40
Figure 9. Maximum Safe Operating Area.
5
4 SINGLE PULSE
RθJA =See note 1b
TA = 25°C
3
2
1
0
0.01
0.1 1 10
SINGLE PULSE TIME (SEC)
100 300
Figure 10. Single Pulse Maximum Power
Dissipation.
1
0.5 D = 0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.0001
0.001
0.01
0.1
t 1, TIME (sec)
1
RθJA (t) = r(t) * R θJA
R θJA = See Note 1b
P(pk)
t1 t 2
TJ - TA = P * R θJA(t)
Duty Cycle, D = t 1/ t 2
10 100
300
Figure 11. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.
FDC6303N Rev.C
4페이지 | |||
구 성 | 총 4 페이지수 | ||
다운로드 | [ FDC6303N.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
FDC6303 | Digital FET/ Dual N-Channel | Fairchild Semiconductor |
FDC6303N | Digital FET/ Dual N-Channel | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |