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부품번호 | FDC653N 기능 |
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기능 | N-Channel Enhancement Mode Field Effect Transistor | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 4 페이지수
November 1997
FDC653N
N-Channel Enhancement Mode Field Effect Transistor
General Description
This N-Channel enhancement mode power field effect
transistors is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMICA cards, and other
battery powered circuits where fast switching, and low in-line
power loss are needed in a very small outline surface mount
package.
Features
5 A, 30 V. RDS(ON) = 0.035 Ω @ VGS = 10 V
RDS(ON) = 0.055 Ω @ VGS = 4.5 V.
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
S
D
D .653
G
D
SuperSOT TM -6 pin 1 D
16
25
34
Absolute Maximum Ratings TA = 25°C unless otherwise note
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage - Continuous
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Maximum Power Dissipation
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
FDC653N
30
±20
5
15
1.6
0.8
-55 to 150
78
30
Units
V
V
A
W
°C
°C/W
°C/W
© 1997 Fairchild Semiconductor Corporation
FDC653N Rev.C
Typical Electrical And Thermal Characteristics
10
ID = 5.0A
8
6
V DS = 5V
15V
10V
4
2
0
0 2 4 6 8 10 12
Qg , GATE CHARGE (nC)
14
Figure 7. Gate Charge Characteristics.
1000
500
Ciss
Coss
200
100
50
0.1
f = 1 MHz
VGS = 0V
Crss
0.3 1 3 10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 8. Capacitance Characteristics.
30
30
10 RDS(ON) LIMIT
3
1
0.3
VGS = 10V
0.1 SINGLE PULSE
RθJA = See Note 1b
0.03 TA = 25°C
100us
1ms
10ms
100ms
1s
DC
0.01
0.1 0.2
0.5 1
2
5 10
VDS , DRAIN-SOURCE VOLTAGE (V)
30
50
5
4 SINGLE PULSE
RθJA =See note 1b
TA = 25°C
3
2
1
0
0.01
0.1 1 10
SINGLE PULSE TIME (SEC)
100 300
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
0.5 D = 0.5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.01
0.0001
0.001
0.01
0.1
t 1, TIME (sec)
1
RθJA (t) = r(t) * R θJA
R θJA = See Note 1b
P(pk)
t1 t 2
TJ - TA = P * R θJA(t)
Duty Cycle, D = t 1/ t 2
10 100
300
Figure 11. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal
response will change depending on the circuit board design.
FDC653N Rev.B
4페이지 | |||
구 성 | 총 4 페이지수 | ||
다운로드 | [ FDC653N.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
FDC653 | N-Channel Enhancement Mode Field Effect Transistor | Fairchild Semiconductor |
FDC653N | N-Channel Enhancement Mode Field Effect Transistor | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |