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부품번호 | FDD603AL 기능 |
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기능 | N-Channel Logic Level Enhancement Mode Field Effect Transistor | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 8 페이지수
July 1999
FDD603AL
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
This N-Channel logic level enhancement mode power
field effect transistor is produced using Fairchilds
proprietary, high cell density, DMOS technology. This
very high density process is tailored to minimize on-
state resistance. These devices are particularly suited
for low voltage applications such as DC/DC converters
and high efficiency switching circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
Applications
DC/DC converters
Motor drives
Features
33 A, 30 V. RDS(ON) = 0.023 Ω @ VGS = 10 V
RDS(ON) = 0.037 Ω @ VGS = 4.5 V.
Critical DC electrical parameters specified at elevated
temperature.
Rugged avalanche-rated internal source-drain diode
can eliminate the need for external Zener Diode.
High density cell design for extremely low RDS(ON) .
D
D
G
G
S
TO-252
Absolute Maxim um Ratings TC=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
PD
TJ, Tstg
Parameter
Drain-Source Voltage
Gate-Source Voltage
Maximum Drain Current - Continuous
(Note 1)
TA = 25°C
Maximum Drain Current -Pulsed
Maximum Power Dissipation @ TC = 25oC
TA = 25oC
TA = 25oC
(Note 1a)
(Note 1)
(Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
(Note 1)
(Note 1a)
(Note 1b)
S
Ratings
30
±20
33
9.5
80
39
3.2
1.3
-55 to +150
2.5
40
96
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDD603AL
FDD603AL
13’’
Tape Width
16mm
1999 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
°C/W
°C/W
°C/W
Quantity
2500
FDD603AL, Rev. B
Typical Characteristics (continued)
10
I D = 10A
8
6
VDS = 5.0V
10V
20V
4
2
0
0 5 10 15
Q g , GATE CHARGE (nC)
20
Figure 7. Gate-Charge Characteristics.
2000
1000
500
Ciss
Coss
200
100
60
0.1
f = 1 MHz
VGS = 0V
Crss
0.3 1
4 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure 8. Capacitance Characteristics.
200
100
50 Limit
20 R DS(ON)
5
1
VGS = 10V
0.1
SINGLE PULSE
RθJC= 3.2o C/W
TA = 25 °C
1µs
1001µ0sµs
1ms
10ms
DC
0.01
0.1
1
35
10
V DS , DRAIN-SOURCE VOLTAGE (V))
30
50
60
SINGLE PULSE
RθJA = 96oC/W
TA = 25oC
40
20
0
0.01
0.1 1 10 100
SINGLE PULSE TIME (SEC)
1000
Figure 9. Maximum Safe Operating Area.
1
0.1
0.01
0.001
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.0001
0.0001
0.001
0.01
0.1
t1 , TIME (sec)
Figure 10. Single Pulse Maximum
Power Dissipation.
R θJA (t) = r(t) * R θJA
R θJA = 96°C/W
P(pk)
t1
t2
TJ - TA = P * R θJA (t)
Duty Cycle, D = t 1 / t 2
1 10 100 300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient themal response will change depending on the circuit board design.
FDD603AL, Rev. B
4페이지 TO-252 Tape and Reel Data and Package Dimensions
TO-252 (FS PKG Code AA)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.300
September 1999, Rev. A
7페이지 | |||
구 성 | 총 8 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
FDD603AL | N-Channel Logic Level Enhancement Mode Field Effect Transistor | Fairchild Semiconductor |
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