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부품번호 | FDG314P 기능 |
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기능 | Digital FET/ P-Channel | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 5 페이지수
July 2000
FDG314P
Digital FET, P-Channel
General Description
This P-Channel enhancement mode field effect
transistor is produced using Fairchild Semiconductor’s
proprietary, high cell density, DMOS technology. This
very high density process is tailored to minimize on-
state resistance at low gate drive conditions. This
device is designed especially for battery power
applications such as notebook computers and cellular
phones. This device has excellent on-state resistance
even at gate drive voltages as low as 2.5 volts.
Applications
• Power Management
• Load switch
• Signal switch
Features
• -0.65 A, -25 V. RDS(ON) = 1.1 Ω @ VGS = -4.5 V
RDS(ON) = 1.5 Ω @ VGS = -2.7 V.
• Very low gate drive requirements allowing direct
operation in 3V cirucuits (VGS(th) <1.5 V).
• Gate-Source Zener for ESD ruggedness
(>6 kV Human Body Model).
• Compact industry standard SC70-6 surface mount
package.
S
D
D
SC70-6
G
D
D
16
25
34
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
PD
TJ, Tstg
ESD
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
(Note 1a)
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf/1500 Ohm)
Ratings
-25
±8
-0.65
-1.8
0.75
0.48
-55 to +150
6.0
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
(Note 1b)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
.14
FDG314P
7’’
260
Tape Width
8mm
Units
V
V
A
W
°C
kV
°C/W
Quantity
3000 units
2000 Fairchild Semiconductor International
FDG314P Rev.C
Typical Characteristics (continued)
5
ID = -0.5A
4
VDS = -5V
-10V
-15V
3
2
1
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
Qg, GATE CHARGE (nC)
Figure 7. Gate-Charge Characteristics.
10
1
0.1
0.01
0.1
RDS(ON) LIMIT
VGS = -4.5V
SINGLE PULSE
RθJA = 260oC/W
TA = 25oC
1ms
10ms
100ms
1s
10s
DC
1 10
-VDS, DRAIN-SOURCE VOLTAGE (V)
100
Figure 9. Maximum Safe Operating Area.
150
f = 1MHz
VGS = 0 V
120
90
60 CISS
30
0
0
COSS
CRSS
5 10 15 20
-VDS, DRAIN TO SOURCE VOLTAGE (V)
25
Figure 8. Capacitance Characteristics.
30
SINGLE PULSE
24
RθJA= 260oC/W
TA= 25oC
18
12
6
0
0.0001 0.001
0.01 0.1
1
10
SINGLE PULSE TIME (SEC)
100 1000
Figure 10. Single Pulse Maximum
Power Dissipation.
1
0.5 D = 0.5
0.2
0.1
0.05
0.01
0.1
0.05
0.01
0.02
Single Pulse
0.005
0.0001
0.001
0.01
0.1
t1 , TIME (sec)
1
R θJA (t) = r(t) * R θJA
R θJA =260°C/W
P(pk)
t1
t2
TJ - TA = P * R θJA (t)
Duty Cycle, D = t 1/ t 2
10 100
300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient themal response will change depending on the circuit board design.
FDG314P Rev.C
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부품번호 | 상세설명 및 기능 | 제조사 |
FDG314P | Digital FET/ P-Channel | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |