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부품번호 | FDS6812 기능 |
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기능 | Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 5 페이지수
November 2001
FDS6812A
Dual N-Channel Logic Level PWM Optimized PowerTrench® MOSFET
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
Features
• 6.7 A, 20 V.
RDS(ON) = 22 mΩ @ VGS = 4.5 V
RDS(ON) = 35 mΩ @ VGS = 2.5 V
• Low gate charge (12 nC typical)
• High performance trench technology for extremely
low RDS(ON)
• High power and current handling capability
DD1
DD1
DD2
DD2
SO-8
Pin 1 SO-8
SS2GS2SS1GG1
5
6 Q1
7
Q2
8
4
3
2
1
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
PD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDS6812A
FDS6812A
13’’
Ratings
20
± 12
6.7
35
2
1.6
1
0.9
–55 to +150
78
40
Tape width
12mm
Units
V
V
A
W
°C
°C/W
°C/W
Quantity
2500 units
©2001 Fairchild Semiconductor Corporation
FDS6812A Rev B (W)
Typical Characteristics
5
ID = 6.7A
4
3
VDS = 5V
15V
10V
2
1
0
0 2 4 6 8 10 12 14
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
10 RDS(ON) LIMIT
1
100µ
1ms
10ms
100ms
1s
10s
DC
VGS = 4.5V
0.1 SINGLE PULSE
RθJA = 135oC/W
TA = 25oC
0.01
0.01
0.1 1 10
VDS, DRAIN-SOURCE VOLTAGE (V)
100
Figure 9. Maximum Safe Operating Area.
1800
1500
1200
900
600
300
0
0
CISS
f = 1MHz
VGS = 0 V
COSS
CRSS
4 8 12 16
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
Figure 8. Capacitance Characteristics.
50
40
30
20
10
0
0.01
0.1
SINGLE PULSE
RθJA = 135°C/W
TA = 25°C
1 10
t1, TIME (sec)
100 1000
Figure 10. Single Pulse Maximum
Power Dissipation.
1
0.1
0.01
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.001
0.0001
SINGLE PULSE
0.001
0.01
0.1
t1, TIME (sec)
1
RθJA(t) = r(t) * RθJA
RθJA = 135oC/W
P(pk)
t1
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
10 100 1000
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
FDS6812A Rev B (W)
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부품번호 | 상세설명 및 기능 | 제조사 |
FDS6812 | Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET | Fairchild Semiconductor |
FDS6812A | Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |