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FDS6815 데이터시트 PDF




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부품번호 FDS6815 기능
기능 Dual P-Channel 2.5V Specified PowerTrench MOSFET
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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FDS6815 데이터시트, 핀배열, 회로
July 1999
ADVANCE INFORMATION
FDS6815
Dual P-Channel 2.5V Specified PowerTrenchTM MOSFET
General Description
These P-Channel 2.5V specified MOSFETs are produced
using a rugged gate version of Fairchild's advanced
PowerTrenchTM process. It has been optimized for
power management applications which require a wide
range of gate drive voltages.
Applications
• Load switch
• Battery protection
• Power management
Features
• -5.5 A, 20 V. RDS(ON) = 0.040 @ VGS = –4.5 V
RDS(ON) = 0.050 @ VGS = –2.5 V
• Extended VGSS range ( ±12V) for battery applications.
• Low gate charge.
• Fast switching speed.
• High performance trench technology for extremely
low RDS(ON).
• High power and current handling capability.
D2
D2
D1
D1
SO-8
G2
S2
G1
S1
Absolute Maximum Ratings TA=25oC unless otherwise noted
Symbol
VDSS
VGSS
ID
PD
Parameter
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
TJ, Tstg
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
RθJC Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
FDS6815
FDS6815
13’’
54
63
72
81
Ratings
20
±12
5.5
50
2.0
1.6
1.0
0.9
-55 to +150
78
40
Tape Width
12mm
Units
V
V
A
W
°C
°C/W
°C/W
Quantity
2500 units
1999 Fairchild Semiconductor Corporation
FDS6815 Rev. A




FDS6815 pdf, 반도체, 판매, 대치품
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
T
P0
D0
K0
Wc
B0
E1
F
E2
W
Tc
A0 P1 D1
User Direction of Feed
Dimensions are in millimeter
Pkg type
A0
B0
W
SOIC(8lds) 6.50
(12mm)
+/-0.10
5.30
+/-0.10
12.0
+/-0.3
D0 D1 E1 E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
10.25
min
F P1
5.50
+/-0.05
8.0
+/-0.1
P0
4.0
+/-0.1
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum
Typical
component
cavity
B0 center line
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
Typical
component
A0 center line
SOIC(8lds) Reel Configuration: Figure 4.0
Sketch B (Top View)
Component Rotation
K0
2.1
+/-0.10
T
0.450
+/-
0.150
Wc
9.2
+/-0.3
Tc
0.06
+/-0.02
0.5mm
maximum
0.5mm
maximum
Sketch C (Top View)
Component lateral movement
W1 Measured at Hub
Dim A
Max
Dim A
max
Dim N
See detail AA
7” Diameter Option
B Min
Dim C
See detail AA
Dim D
W3 min
13” Diameter Option
W2 max Measured at Hub
Tape Size
Reel
Option
12mm
7” Dia
12mm
13” Dia
Dimensions are in inches and millimeters
Dim A
7.00
177.8
13.00
330
Dim B
0.059
1.5
0.059
1.5
Dim C
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
Dim D
0.795
20.2
0.795
20.2
Dim N
5.906
150
7.00
178
Dim W1
0.488 +0.078/-0.000
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
DETAIL AA
Dim W2
0.724
18.4
0.724
18.4
Dim W3 (LSL-USL)
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
© 1998 Fairchild Semiconductor Corporation
November 1998, Rev. A

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