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부품번호 | FDS6912A 기능 |
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기능 | Dual N-Channel/ Logic Level/ PowerTrenchTM MOSFET | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 4 페이지수
June 1998
FDS6912A
Dual N-Channel, Logic Level, PowerTrenchTM MOSFET
General Description
These N-Channel Logic Level MOSFETs are
produced using Fairchild Semiconductor's
advanced PowerTrench process that has been
especially tailored to minimize the on-state
resistance and yet maintain superior switching
performance.
These devices are well suited for low voltage and
battery powered applications where low in-line
power loss and fast switching are required.
Features
6 A, 30 V. RDS(ON) = 0.028 Ω @ VGS = 10 V
RDS(ON) = 0.035 Ω @ VGS = 4.5 V.
Fast switching speed.
Low gate charge (typical 9 nC).
High performance trench technology for extremely low
RDS(ON).
High power and current handling capability.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
D2
D2
D1
D1
F6D9S12A
SO-8
G2
S2
pin 1
G1
S1
SO-8
SOT-223
SOIC-16
54
63
72
81
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a)
RθJC Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
FDS6912A
30
±20
6
20
2
1.6
0.9
-55 to 150
78
40
Units
V
V
A
W
°C
°C/W
°C/W
FDS6912A Rev.C
Typical Electrical Characteristics
10
ID = 6A
8
6
VDS = 5V
10V
15V
4
2
0
0 3 6 9 12 15 18
Qg , GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
100
50
10 RDS(ON) LIMIT
2
0.5
VGS =10V
SINGLE PULSE
0.05 RθJA = 135°C/W
TA A= 25°C
100us
1ms
1001m0ms s
1s
D1C0s
0.01
0.1
0.5 1
2
5 10
VDS , DRAIN-SOURCE VOLTAGE (V)
30
50
1500
500
C iss
200
100
50 f = 1 MHz
V GS = 0 V
Coss
Crss
0.1 0.2
0.5 1
2
5 10
VDS , DRAIN TO SOURCE VOLTAGE (V)
30
Figure 8. Capacitance Characteristics.
30
25
20
15
10
5
0
0.01
SINGLE PULSE
RθJA =135 °C/W
TA = 25°C
0.1 0.5
10
SINGLE PULSE TIME (SEC)
50 100 300
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.002
0.001
0.0001
0.001
0.01
0.1
t1 , TIME (sec)
1
R θJA (t) = r(t) * R θJA
R θJA =135° C/W
P(pk)
t1 t 2
TJ - TA = P * RθJA (t)
Duty Cycle, D = t1 /t2
10 100 300
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1c.
Transient thermal response will change depending on the circuit board design.
FDS6912A Rev.C
4페이지 | |||
구 성 | 총 4 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
FDS6912 | Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET | Fairchild Semiconductor |
FDS6912A | Dual N-Channel/ Logic Level/ PowerTrenchTM MOSFET | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |