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PDF FDS8928A Data sheet ( Hoja de datos )

Número de pieza FDS8928A
Descripción Dual N & P-Channel Enhancement Mode Field Effect Transistor
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDS8928A Hoja de datos, Descripción, Manual

July 1998
FDS8928A
Dual N & P-Channel Enhancement Mode Field Effect Transistor
General Description
These dual N- and P -Channel enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as notebook computer power
management and other battery powered circuits where fast
switching, low in-line power loss, and resistance to
transients are needed.
Features
N-Channel 5.5 A,30 V, RDS(ON)=0.030 @ VGS=4.5 V
RDS(ON)=0.038 @ VGS=2.5 V.
P-Channel -4 A,-20 V, RDS(ON)=0.055 @ VGS=-4.5 V
RDS(ON)=0.072 @ VGS=-2.5 V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual (N & P-Channel) MOSFET in surface mount package.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
D2
D2
D1
D1
F8D9S28A
SO-8
G2
S2
pin 1
G1
S1
54
63
72
81
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current - Continuous
- Pulsed
(Note 1a)
PD Power Dissipation for Dual Operation
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient (Note 1a)
Thermal Resistance, Junction-to-Case (Note 1)
© 1998 Fairchild Semiconductor Corporation
N-Channel
30
8
5.5
20
2
1.6
1
0.9
-55 to 150
P-Channel
-20
-8
-4
-20
78
40
Units
V
V
A
W
°C
°C/W
°C/W
FDS8928A Rev. B

1 page




FDS8928A pdf
Typical Electrical Characteristics: N-Channel (continued)
5
ID = 5.5A
4
3
2
1
0
05
VDS = 5V
10V
15V
10 15
Qg , GATE CHARGE (nC)
20
Figure 7. Gate Charge Characteristics.
25
3000
1000
500
200
C iss
C oss
80 f = 1 MHz
VGS = 0V
Crss
30
0.1
0.4 1 2
5 10
VDS , DRAIN TO SOURCE VOLTAGE (V)
30
Figure 8. Capacitance Characteristics.
50
10 RDS(ON) LIMIT
3
1
0.3
0.1 VGS = 4.5V
SINGLE PULSE
0.03 RθJA =135 °C/W
TA = 25°C
0.01
0.1 0.2
0.5
1
2
1m10s0us
10ms
100ms
1s
10s
DC
5 10 20 30
VDS , DRAI N-SOURCE VOLTAGE (V)
50
Figure 9. Maximum Safe Operating Area.
30
25
20
15
10
5
0
0.01
SINGLE PULSE
RθJA =135 °C/W
TA = 25°C
0.1 0.5
10
SINGLE PULSE TIME (SEC)
50 100 300
Figure 10. Single Pulse Maximum Power
Dissipation.
FDS8928A Rev. B

5 Page





FDS8928A arduino
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A

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