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PDF FDV302 Data sheet ( Hoja de datos )
| Número de pieza | FDV302 | |
| Descripción | Digital FET/ P-Channel | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 1997
FDV302P
Digital FET, P-Channel
General Description
This P-Channel logic level enhancement mode field effect
transistor is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for digital transistors. Since
bias resistors are not required, this one P-channel FET can
replace several digital transistors with different bias resistors
such as the DTCx and DCDx series.
SOT-23
Mark:302
SuperSOTTM-6
SuperSOTTM-8
Features
-25 V, -0.12 A continuous, -0.5 A Peak.
RDS(ON) = 13 Ω @ VGS= -2.7 V
RDS(ON) = 10 Ω @ VGS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. VGS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Compact industry standard SOT-23 surface mount
package.
Replace many PNP digital transistors (DTCx and DCDx)
with one DMOS FET.
SO-8
SOT-223
SOIC-16
D
Absolute Maximum Ratings TA = 25oC unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain Current
- Continuous
- Pulsed
PD
TJ,TSTG
ESD
Maximum Power Dissipation
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient
© 1997 Fairchild Semiconductor Corporation
GS
FDV302P
-25
-8
-0.12
-0.5
0.35
-55 to 150
6.0
357
Units
V
V
A
W
°C
kV
°C/W
FDV302P REV. F
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet FDV302.PDF ] | |
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