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FAN4803 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 FAN4803은 전자 산업 및 응용 분야에서
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부품번호 FAN4803 기능
기능 8-Pin PFC and PWM Controller Combo
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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FAN4803 데이터시트, 핀배열, 회로
www.fairchildsemi.com
FAN4803
8-Pin PFC and PWM Controller Combo
Features
• Internally synchronized PFC and PWM in one 8-pin IC
• Proprietary one-pin voltage error amplifier with advanc
input current shaping technique
• Peak or average current, continuous boost, leading edge
PFC (Input Current Shaping Technology)
• High efficiency trailing-edge current mode PWM
• Low supply currents; start-up: 150µA typ., operating:
2mA typ.
• Synchronized leading and trailing edge modulation
• Reduces ripple current in the storage capacitor between
the PFC and PWM sections
• Overvoltage, UVLO, and brownout protection
• PFC VCCOVP with PFC Soft Start
General Description
The FAN4803 is a space-saving controller for power factor
corrected, switched mode power supplies that offers very
low start-up and operating currents.
Power Factor Correction (PFC) offers the use of smaller, lower
cost bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply fully compli-
ant to IEC1000-3-2 specifications. The FAN4803 includes
circuits for the implementation of a leading edge, average
current “boost” type PFC and a trailing edge, PWM.
The FAN4803-1’s PFC and PWM operate at the same
frequency, 67kHz. The PFC frequency of the FAN4803-2 is
automatically set at half that of the 134kHz PWM. This
higher frequency allows the user to design with smaller
PWM components while maintaining the optimum operating
frequency for the PFC. An overvoltage comparator shuts
down the PFC section in the event of a sudden decrease in
load. The PFC section also includes peak current limiting for
enhanced system reliability.
Block Diagram
VEAO
4
7V
35µA
+ PFC OFF
COMP
–1
M1 M2
M7
M3
R1
7
VCC
17.5V
16.2V
C1
30pF
M4
ISENSE
3
–1V
ONE PIN ERROR AMPLIFIER
+ PFC ILIMIT
VCC
–4
PFC/PWM UVLO
+
COMP
VREF
26k
VDC
5
40k
ILIMIT
6
1.2V
OSCILLATOR
PFC – 67kHz
PWM – 134kHz
DUTY CYCLE
LIMIT
PWM COMPARATOR
COMP
+
COMP
+
M6
1.5V
DC ILIMIT
+
+ VCC OVP
COMP
REF
VREF
GND
2
PFC
CONTROL
LOGIC
SOFT START
PFC OUT
1
LEADING
EDGE PFC
TRAILING
EDGE PWM
PWM
CONTROL
LOGIC
PWM OUT
8
REV. 1.2.3 11/2/04




FAN4803 pdf, 반도체, 판매, 대치품
FAN4803
PRODUCT SPECIFICATION
Functional Description
The FAN4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a syn-
chronized Pulse Width Modulation (PWM) controller. It is
distinguished from earlier combo controllers by its low pin
count, innovative input current shaping technique, and very
low start-up and operating currents. The PWM section is
dedicated to peak current mode operation. It uses conven-
tional trailing-edge modulation, while the PFC uses leading-
edge modulation. This proprietary Leading Edge/Trailing
Edge (LETE) modulation technique helps to minimize ripple
current in the PFC DC buss capacitor.
The FAN4803 is offered in two versions. The FAN4803-1
operates both PFC and PWM sections at 67kHz, while the
FAN4803-2 operates the PWM section at twice the fre-
quency (134kHz) of the PFC. This allows the use of smaller
PWM magnetics and output filter components, while mini-
mizing switching losses in the PFC stage.
In addition to power factor correction, several protection fea-
tures have been built into the FAN4803. These include soft
start, redundant PFC over-voltage protection, peak current
limiting, duty cycle limit, and under voltage lockout
(UVLO). See Figure 12 for a typical application.
Detailed Pin Descriptions
VEAO
This pin provides the feedback path which forces the PFC
output to regulate at the programmed value. It connects to
programming resistors tied to the PFC output voltage and is
shunted by the feedback compensation network.
ISENSE
This pin ties to a resistor or current sense transformer which
senses the PFC input current. This signal should be negative
with respect to the IC ground. It internally feeds the pulse-
by-pulse current limit comparator and the current sense feed-
back signal. The ILIMIT trip level is –1V. The ISENSE feed-
back is internally multiplied by a gain of four and compared
against the internal programmed ramp to set the PFC duty
cycle. The intersection of the boost inductor current
downslope with the internal programming ramp determines
the boost off-time.
VDC
This pin is typically tied to the feedback opto-collector. It is
tied to the internal 5V reference through a 26kresistor and
to GND through a 40kresistor.
ILIMIT
This pin is tied to the primary side PWM current sense resis-
tor or transformer. It provides the internal pulse-by-pulse
current limit for the PWM stage (which occurs at 1.5V) and
the peak current mode feedback path for the current mode
control of the PWM stage. The current ramp is offset inter-
nally by 1.2V and then compared against the opto feedback
voltage to set the PWM duty cycle.
PFC OUT and PWM OUT
PFC OUT and PWM OUT are the high-current power driv-
ers capable of directly driving the gate of a power MOSFET
with peak currents up to ±1A. Both outputs are actively held
low when VCC is below the UVLO threshold level.
VCC
VCC is the power input connection to the IC. The VCC start-
up current is 150µA . The no-load ICC current is 2mA. VCC
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the operating
frequency and the MOSFET gate charge (Qg), average
PFC and PWM output currents can be calculated as IOUT =
Qg x F. The average magnetizing current required for any
gate drive transformers must also be included. The VCC pin
is also assumed to be proportional to the PFC output voltage.
Internally it is tied to the VCCOVP comparator (16.2V)
providing redundant high-speed over-voltage protection
(OVP) of the PFC stage. VCC also ties internally to the
UVLO circuitry, enabling the IC at 12V and disabling it at
9.1V. VCC must be bypassed with a high quality ceramic
bypass capacitor placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
FAN4803.
VCC is typically produced by an additional winding off the
boost inductor or PFC Choke, providing a voltage that is pro-
portional to the PFC output voltage. Since the VCCOVP max
voltage is 16.2V, an internal shunt limits VCC overvoltage to
an acceptable value. An external clamp, such as shown in
Figure 1, is desirable but not necessary.
VCC
1N4148
1N4148
1N5246B
GND
Figure 1. Optional VCC Clamp
VCC is internally clamped to 16.7V minimum, 18.3V maxi-
mum. This limits the maximum VCC that can be applied to
the IC while allowing a VCC which is high enough to trip the
VCCOVP. The max current through this zener is 10mA.
External series resistance is required in order to limit the
current through this Zener in the case where the VCC voltage
exceeds the zener clamp level.
4 REV. 1.2.3 11/2/04

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FAN4803 전자부품, 판매, 대치품
PRODUCT SPECIFICATION
RCOMP =
1
2 × π × f × CCOMP
RCOMP =
6.2 8
1
× 30Hz
= 330k
× 16nF
1
CZERO
=
2
×
π
×
f
10
× RCOMP
CZERO
=
6.28
×
1
3Hz
×
=
330k
0.16 µF
FAN4803
Internal Voltage Ramp
The internal ramp current source is programmed by way of
(3) the VEAO pin voltage. Figure 7 displays the internal ramp
current vs. the VEAO voltage. This current source is used to
develop the internal ramp by charging the internal 30pF +12/
–10% capacitor. See Figures 10 and 11. The frequency of the
internal programming ramp is set internally to 67kHz.
PFC Current Sense Filtering
(4) In DCM, the input current wave shaping technique used by
the FAN4803 could cause the input current to run away.
In order for this technique to be able to operate properly
under DCM, the programming ramp must meet the boost
inductor current down-slope at zero amps. Assuming the
programming ramp is zero under light load, the OFF-time
will be terminated once the inductor current reaches zero.
VO
FAN4803
VEAO +
IOUT
220µF
11.3M
RLOAD
667
VEAO
330k
15nF
POWER
STAGE
0.15µF
COMPENSATION
FAN4803
IVEAO
34µA
Figure 4. Voltage Control Loop
0
Power Stage
Overall
Compensation
Network
50
100
150
200
0.1
1 10 100
FREQUENCY (Hz)
Figure 6. Voltage Loop Phase
1000
REV. 1.2.3 11/2/04
60
Power Stage
Overall Gain
40 Compensation
Network Gain
20
0
20
40
60
0.1
1 10 100
FREQUENCY (Hz)
Figure 5. Voltage Loop Gain
1000
50
FF @ 55ºC
40 TYP @ 55ºC
TYP @ ROOM TEMP
30 TYP @ 155ºC
SS @ 155ºC
20
10
0
0 1234567
VEAO (V)
Figure 7. Internal Ramp Current vs. VEAO
7

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