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PDF FAN5250 Data sheet ( Hoja de datos )
| Número de pieza | FAN5250 | |
| Descripción | Mobile Processor Core-Voltage Regulator | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.fairchildsemi.com
FAN5250
Mobile Processor Core-Voltage Regulator
Features
• High efficiency over wide load range
• Non dissipative current-sense; uses MOSFET RDS(ON) or
can use optional Current-Sense resistor for greater
precision
• Overcurrent protection
• Powerful drivers for N-Channel MOSFETs with adaptive
dead time
• Precision core voltage control
• Remote “Kelvin” sensing
• Summing current-mode control with programmable
Active Droop for Optimum Transient Response and
Lower Processor Power Dissipation
• 5-Bit Digital Output Voltage Selection
• Wide Range output voltage: 0.6 VDC to 1.0 VDC in
25mV Steps, and from 1.0 VDC to 1.75 VDC in 50mV
Steps
• “On-the-Fly” VID code change with programmable slew
rate
• Alternative input to set output voltage during start-up or
power saving modes
• Forced continuous conduction mode of operation
• Output voltage (Power-Good) monitor
• No negative core voltage on turn-off
• Over-Voltage, Under-Voltage and Over-Current fault
monitors
• Selectable 300/600kHz Switching Frequency
Applications
• Transmeta’s Crusoe™ CPU core power
• Intel P3-M™ processor (IMVP-2)
Description
The FAN5250 is a single output power controller to power
mobile CPU cores. The FAN5250 includes a 5-bit digital-to-
analog converter (DAC) that adjusts the core PWM output
voltage from 0.6VDC to 1.75VDC, and may be changed
during operation. Special measures are taken to allow the
output to transition with controlled slew rate to comply with
Transmeta’s LongRun™ and Intel’s P3-M Speed-Step™
requirements. The FAN5250 includes a precision reference,
and a proprietary architecture with integrated compensation
providing excellent static and dynamic core voltage regula-
tion.
With nominal currents, the controller operates at a selectable
frequency of 300kHz or 600kHz. At light loads, when the
filter inductor current becomes discontinuous, the controller
operates in a hysteretic mode dramatically improving system
efficiency. The hysteretic mode of operation can be inhibited
by the FPWM control pin.
The FAN5250 monitors the output voltage and issues a
PGOOD (Power-Good) when soft start is completed and the
output is in regulation. A built-in over-voltage protection
(OVP) forces the lower MOSFET on to prevent output volt-
ages from exceeding 1.9V. Undervoltage protection latches
the chip off when the output drops below 75% of the set
value. The PWM controller's overcurrent circuitry monitors
the converter load by sensing the voltage drop across the
lower MOSFET. The overcurrent threshold is set by an
external resistor. If precision overcurrent protection is
required, an optional external current-sense resistor may
be used.
LongRun is a trademark of Transmeta Corporation.
REV. 1.1.6 3/12/03
1 page  
FAN5250
Electrical Specifications
(VCC = 5V, VIN = 5V–24V, and TA = recommended operating ambient temperature range using circuit of Figure 1,
unless otherwise noted)
Parameter
Power Supplies
VCC Current
VIN Current
UVLO Threshold
Regulator / Control Functions
Output Voltage
Initial Accuracy
Static Load Regulation
Error Amplifier Gain
Error Amplifier GBW
Error Amplifier Slew Rate
ILIM Voltage
Over-voltage Threshold
Over-voltage Protection Delay
Under-voltage Shutdown
Under-voltage Delay
EN, input threshold
Output Drivers
HDRV Output Resistance
LDRV Output Resistance
Oscillator
Frequency
Ramp Amplitude, pk-pk
Ramp Offset
Ramp Gain
Reference, DAC and Soft-Start
VID input threshold
VID pull-up current
DAC output accuracy
Conditions
Operating, CL = 10pF
Shut-down (EN = 0)
Operating
Shut-down (EN = 0)
Rising VCC
Falling
per Table 1. Output
Voltage VID
RILIM = 30KΩ
Disabled during VID code
change
Logic LOW
Logic HIGH
Sourcing
Sinking
Sourcing
Sinking
FREQ = HIGH
FREQ = LOW
VIN = 16V
Ramp amplitude
VIN
Logic LOW
Logic HIGH
to internal 2.5V reference
Min. Typ. Max. Units
2.7 3.2 mA
6 30 µA
12 20 µA
1 µA
4.3 4.65 4.75
V
4.1 4.35 4.45
V
0.6 1.75 V
-1 1 % VID
-2 2 % VID
86 dB
2.7 MHz
1 V/µS
0.89 0.91 V
1.9 1.95 2.0
V
1.6 3.2 µS
72 75 78 % VID
1.2 1.6 µS
1.2 V
2V
3.8 5
1.6 3
3.8 5
0.8 1.5
Ω
Ω
Ω
Ω
255 300 345 KHz
510 600 690 KHz
2V
0.5 V
125 mV/V
1.21 V
1.62 V
12 µA
-1 1 %
REV. 1.1.6 3/12/03
5
5 Page 
FAN5250
1.2 upper limit
VDROOP
VCPU = 1.35V
1
lower limit
ILOAD
IMAX
Figure 8. Active Droop
Additionally, the CPU power dissipation is also slightly
reduced as it is proportional to the applied voltage squared
and even slight voltage decrease translates to a measurable
reduction in power dissipated.
ILOAD
Vout
(no droop)
VESR
upper lim
Vout
droop » ESR
lower lim
upper lim
VESR
lower lim
Figure 9. Effect of Active Droop on ESR
The Crusoe processor regulation window including
transients is specified as +5%…–2%. To accommodate the
droop, the output voltage of the converter is raised by about
3.25% at no load as shown below (R24 = 1K and
R25 = 30.1K):
V CORE
16 VCORE+
R24
R25
COUT
Figure 10. Setting the No-Load Output Voltage Rise
The converter response to the load step is shown in Figure
11. At zero load current, the output voltage is raised ~50mV
above nominal value of 1.35V. When the load current
increases, the output voltage droops down approximately
55mV. Due to use of Active Droop, the converter’s output
voltage adaptively changes with the load current allowing
better utilization of the regulation window.
REV. 1.1.6 3/12/03
ICPU = 0A...5.0A
2
Ch1 50mV
Ch2 2.0A
M50µs
Figure 11. Converter Response to 5A Load Step
The current through RSENSE resistor (ISNS) is sampled
shortly after Q2 is turned on. That current is held, and then
injected (with a 1/48 gain) into the inverting path of the error
amp to produce an offset to the sensed output voltage at
VCORE + proportional to the load current.
VDROOP = 100K × -I-L---O-4---8A----D-×----×-R---R-S----ED---N-S---S(--O-E---N----)
VDROOP
=
2083
×
-I-L---O----A----D-----×----R-----D----S---(--O----N----)
RSENSE
(9a)
(9b)
Setting the Current Limit
A ratio of ISNS is also compared to the current established
when a 1.2 V internal reference drives the ILIM pin. The
threshold is determined at the point when the
I---S----N-----S--
8
>
I---L---I--M-------×-----4-
3
Since
therefore,
ISNS = -I-L---O----A----D-----×----R-----D----S---(--O----N----)
RSENSE
ILIMIT
=
-1---.--2---V---
RLIM
×
43--
×
-8----×-----(---1---0---0-----+-----R-----S---E---N----S----E----)
RDS(ON)
(10)
Since the tolerance on the current limit is largely dependent
on the ratio of the external resistors it is fairly accurate if the
voltage drop on the Switching Node side of RSENSE is an
accurate representation of the load current. When using the
MOSFET as the sensing element, the variation of RDS(ON)
causes proportional variation in the ISNS. This value not
only varies from device to device, but also has a typical
junction temperature coefficient of about 0.4%/°C
(consult the MOSFET datasheet for actual values), so the
actual current limit set point will decrease proportional to
increasing MOSFET die temperature. The same discussion
applies to the VDROOP calculation, which has an additional
initial error of ±20% due to its value being determined by
a ratio between RSENSE and the internal 100K resistor.
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet FAN5250.PDF ] | |
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