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부품번호 | EPM7256AE 기능 |
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기능 | Programmable Logic Device | ||
제조업체 | Altera Corporation | ||
로고 | |||
전체 30 페이지수
October 2002, ver. 4.3
Includes
® MAX 7000AE
MAX 7000A
Programmable Logic
Device
Data Sheet
Features...
f
■ High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX®) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
■ Enhanced ISP features
– Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
– ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.
Altera Corporation
DS-M7000A-4.3
1
MAX 7000A Programmable Logic Device Data Sheet
The MAX 7000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density integration of SSI, MSI, and LSI logic
functions. It easily integrates multiple devices including PALs, GALs, and
22V10s devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA,
PQFP, and TQFP packages. See Table 3 and Table 4.
Table 3. MAX 7000A Maximum User I/O Pins Note (1)
Device
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
44-Pin PLCC 44-Pin TQFP 49-Pin Ultra 84-Pin PLCC
FineLine
BGA (2)
36 36
36 36 41
68
68
100-Pin
TQFP
68
84
84
84
84
100-Pin
FineLine
BGA (3)
68
84
84
84
Table 4. MAX 7000A Maximum User I/O Pins Note (1)
Device
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
144-Pin TQFP 169-Pin Ultra 208-Pin PQFP 256-Pin BGA 256-Pin FineLine
FineLine BGA (2)
BGA (3)
100 100
100 100
100
120 164 164
120 164 164
120
176 212
212
Notes to tables:
(1) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/O
pins become JTAG pins.
(2) All Ultra FineLine BGA packages are footprint-compatible via the SameFrameTM feature. Therefore, designers can
design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.
Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more
details.
(3) All FineLine BGA packages are footprint-compatible via the SameFrame feature. Therefore, designers can design a
board to support a variety of devices, providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 15 for more details.
4 Altera Corporation
4페이지 Figure 1. MAX 7000A Device Block Diagram
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
MAX 7000A Programmable Logic Device Data Sheet
INPUT/GCLRn
6 or 10 Output Enables (1)
2 to 16 I/O
2 to 16 LAB A
I/O 2 to 16
Control
Block
Macrocells
1 to 16
36
16
6 or 10 Output Enables (1)
LAB B 2 to 16
36 Macrocells
17 to 32
16
2 to 16 I/O
Control
Block
2 to 16 I/O
2 to 16 I/O
6
2 to 16 LAB C
2 to 16
PIA
2 to 16
LAB D 2 to 16
6
I/O 2 to 16
Control
Block
Macrocells
33 to 48
36
16
36 Macrocells
49 to 64
16
2 to 16 I/O
Control
Block
2 to 16 I/O
6
2 to 16
2 to 16
6
Note:
(1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables.
EPM7512AE devices have 10 output enables.
Logic Array Blocks
The MAX 7000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
■ 36 signals from the PIA that are used for general logic inputs
■ Global controls that are used for secondary register functions
■ Direct input paths from I/O pins to the registers that are used for fast
setup times
Altera Corporation
7
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