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PDF DS90C383 Data sheet ( Hoja de datos )
| Número de pieza | DS90C383 | |
| Descripción | +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1999
DS90C383/DS90CF384
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link— 65 MHz, +3.3V LVDS Receiver
24-Bit Flat Panel Display (FPD) Link— 65 MHz
General Description
The DS90C383 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CF384 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 65 MHz, 24 bits of RGB data and 3
bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY) are transmitted at a rate of 455 Mbps per LVDS data
channel. Using a 65 MHz clock, the data throughputs is 227
Mbytes/sec. The transmitter is offered with programmable
edge data strobes for convenient interface with a variety of
graphics controllers. The transmitter can be programmed for
Rising edge strobe or Falling edge strobe through a dedi-
cated pin. A Rising edge transmitter will inter-operate with a
Falling edge receiver (DS90CF384) without any translation
logic. The DS90CF384 is also offered in 64 ball, 0.8mm fine
pitch ball grid array(FBGA) package which provides a 44 %
reduction in PCB footprint (available Q3, 1999).
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clock support
n Programmable transmitter (DS90C383) strobe select
(Rising or Falling edge strobe)
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption < 250 mW (typ)
n Power-down mode (< 0.5 mW total)
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 227 Megabytes/sec bandwidth
n Up to 1.8 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package.
n DS90CF384 also available in 64 ball, 0.8mm fine pitch
ball grid array(FBGA) package
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating >7 kV
n Operating Temperature: −40˚C to +85˚C
Block Diagrams
Application
DS012887-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012887
www.national.com
1 page  
Receiver Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CMOS/TTL High-to-Low Transition Time (Figure 4 )
Receiver Input Strobe Position for Bit 0 (Figure 18 )
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 5) (Figure 19 )
RxCLK OUT Period (Figure 8)
RxCLK OUT High Time (Figure 8 )
RxCLK OUT Low Time (Figure 8)
RxOUT Setup to RxCLK OUT (Figure 8 )
RxOUT Hold to RxCLK OUT (Figure 8 )
RxCLK IN to RxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 10 )
Receiver Phase Lock Loop Set (Figure 12 )
Receiver Power Down Delay (Figure 16 )
f = 65 MHz
f = 65 MHz
f = 65 MHz
Min
0.7
2.9
5.1
7.3
9.5
11.7
13.9
400
15
7.3
3.45
2.5
2.5
5.0
Typ
2.2
2.2
1.1
3.3
5.5
7.7
9.9
12.1
14.3
T
8.6
4.9
6.9
5.7
7.1
Max Units
5.0 ns
5.0 ns
1.4 ns
3.6 ns
5.8 ns
8.0 ns
10.2 ns
12.4 ns
14.6 ns
ps
50 ns
ns
ns
ns
ns
9.0 ns
10 ms
1 µs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows for LVDS interconnect skew, inter-symbol interfer-
ence (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS012887-3
5 www.national.com
5 Page 
AC Timing Diagrams (Continued)
FIGURE 18. Receiver LVDS Input Strobe Position
DS012887-25
11 www.national.com
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet DS90C383.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90C383 | +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz | National Semiconductor |
| DS90C383 | DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display |  Texas Instruments |
| DS90C383 | DS90C383/F384 3.3VProg LVDS Trans 24Bit FPD 65MHz3.3VLVDS Rcvr 24Bit FPD 65MHz (Rev. A) | Texas Instruments |
| DS90C383A | +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz | National Semiconductor |
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