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PDF DS92LV1212TMSA Data sheet ( Hoja de datos )
| Número de pieza | DS92LV1212TMSA | |
| Descripción | 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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April 1999
DS92LV1212
16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer
with Embedded Clock Recovery
General Description
The DS92LV1212 is an upgrade of the DS92LV1210. It
maintains all of the features of the DS92LV1210 with the ad-
ditional capability of locking to the incoming data stream
without the need of SYNC patterns. This makes the
DS92LV1212 useful in applications where the Deserializer
must be operated “open-loop” — without a feedback path
from the Deserializer to the Serializer. The DS92LV1212 is
designed to be used with the DS92LV1021 Bus LVDS Serial-
izer. The DS92LV1212 receives a Bus LVDS serial data
stream and transforms it into a 10-bit wide parallel data bus
and separate clock. The reduced cable, PCB trace count
and connector size saves cost and makes PCB layout
easier. Clock-to-data and data-to-data skews are eliminated
since one input receives both clock and data bits serially.
The powerdown pin is used to save power by reducing the
supply current when the device is not in use. The Deserial-
izer will establish lock to a synchronization pattern within
specified lock times but it can also lock to a data stream with-
out SYNC patterns.
Features
n Clock recovery without SYNC patterns-random lock
n Guaranteed transition every data transfer cycle
n Chipset (Tx + Rx) power consumption < 300mW (typ) @
40MHz
n Single differential pair eliminates multi-channel skew
n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
or UTOPIA I Interface
n Synchronization mode and LOCK indicator
n Flow-through pinout for easy PCB layout
n High impedance on receiver inputs when power is off
n Programmable edge trigger on clock
n Footprint compatible with DS92LV1210
n Small 28-lead SSOP package-MSA
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100982
DS100982-1
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
Bus LVDS Receiver Input
Voltage
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 seconds)
+260˚C
Maximum Package Power Dissipation Capacity
@ 25˚C Package:
28L SSOP
1.27 W
Package Derating:
28L SSOP
ESD Rating (HBM)
10.2 mW/˚C above +25˚C
>2.5kV
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Free Air
Temperature (TA)
Receiver Input Range
Supply Noise Voltage
(VCC)
Min Nom Max Units
3.0 3.3 3.6 V
−40 +25 +85 ˚C
0 2.4 V
100 mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ Max Units
DESERIALIZER CMOS/TTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins
ROUT, RCLK, LOCK = outputs)
VIH High Level Input Voltage
VIL Low Level Input Voltage
VCL Input Clamp Voltage
ICL = −18 mA
IIN Input Current
VIN = 0V or 3.6V
VOH
High Level Output Voltage
IOH = −9 mA
VOL
Low Level Output Voltage
IOL = 9 mA
IOS Output Short Circuit Current VOUT = 0V
IOZ TRI-STATE Output Current PWRDN or REN = 0.8V, VOUT = 0V or VCC
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
2.0
GND
−10
2.1
GND
−15
−10
−0.62
±2
2.93
0.33
−38
±0.4
VCC
0.8
−1.5
+10
VCC
0.6
−85
+10
V
V
V
µA
V
V
mA
µA
VTH
Differential Threshold High
Voltage
VCM = +1.1V
+6 +100 mV
VTL Differential Threshold Low
Voltage
IIN Input Current
VIN = +2.4V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
−100 −12
mV
−10 ±5 +10 µA
−10 ±5 +10 µA
ICCR
Deserializer Supply Current
Worst Case
CL = 15 pF
Figure 1
f = 40 MHz
f = 16 MHz
47 60 mA
30 40 mA
ICCXR
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
0.34
1.0
mA
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions Min Typ
tRFCP
tRFDC
fRef
tRFTT
REFCLK Period
REFCLK Duty Cycle
REFCLK Frequency
REFCLK Transition Time
25
0.95/tRCP
T
50
tRCP
3
Max
62.5
1.05/tRCP
6
Units
ns
%
ns
5 www.national.com
5 Page 
Application Information (Continued)
and lowers threshold margin at the Deserializers. Deserial-
izer devices should be placed no more than 1 inch from the
slot connector.
Transmission Media
The Serializer and Deserializer are designed for data trans-
mission over a multi-drop bus. Multi-drop buses use a single
Serializer and multiple Deserializer devices. Since the Seri-
alizer can be driving from any point on the bus, the bus must
be terminated at both ends. For example, a 100 Ohm differ-
ential bus must be terminated at each end with 100 Ohms
lowering the DC impedance that the Serializer must drive to
50 Ohms. This load is further lowered by the addition of mul-
tiple Deserializers. Adding up to 20 Deserializers to the bus
(depending upon spacing) will lower the total load to about
27 Ohms (54 Ohm bus). The Serializer is designed for DC
loads between 27 and 100 Ohms.
The Serializer and Deserializer can also be used in
point-to-point configuration of a backplane, PCB trace or
through a twisted pair cable. In point-to-point configurations
the transmission media need only be terminated at the re-
ceiver end. In the point-to-point configuration the potential of
offsetting the ground levels of the Serializer vs. the Deserial-
izer must be considered. Bus LVDS provides a plus / minus
one volt common mode range at the receiver inputs.
DS100982-26
The DS92LV1212 can be “Hot Inserted” into operating serial busses without interrupting bus communication. The random lock feature allows the DS92LV1212
to synchronize to the bus traffic and receive data.
FIGURE 10. Random Lock Allows Hot Insertion into Serial Busses
Pin Diagram
DS92LV1212TMSA - Deserializer
Deserializer Pin Description
Pin Name
ROUT
I/O No.
O 15–19,
24–28
DS100982-19
Description
Data Output. ±9 mA CMOS level outputs.
11 www.national.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet DS92LV1212TMSA.PDF ] | |
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