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PDF DS92LV16TVHG Data sheet ( Hoja de datos )
| Número de pieza | DS92LV16TVHG | |
| Descripción | 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 2002
DS92LV16
16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz
General Description
The DS92LV16 Serializer/Deserializer (SERDES) pair trans-
parently translates a 16–bit parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 16-bit, or less bus over PCB
traces and cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by nar-
rowing data paths that in turn reduce PCB layers, cable
width, and connector size and pins.
This SERDES pair includes built-in system and device test
capability. The line loopback and local loopback features
provide the following functionality: the local loopback en-
ables the user to check the integrity of the transceiver from
the local parallel-bus side and the system can check the
integrity of the data transmission line by enabling the line
loopback.
The DS92LV16 incorporates BLVDS signaling on the high-
speed I/O. BLVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. The equal and opposite currents through the
differential data path control EMI by coupling the resulting
fringing fields together.
Features
n 25–80 MHz 16:1/1:16 serializer/deserializer (2.56Gbps
full duplex throughput)
n Independent transmitter and receiver operation with
separate clock, enable, power down pins
n Hot plug protection (power up high impedance) and
synchronization (receiver locks to random data)
n Wide +/−5% reference clock frequency tolerance for
easy system design using locally-generated clocks
n Line and local loopback modes
n Robust BLVDS serial transmission across backplanes
and cables for low EMI
n No external coding required
n Internal PLL, no external PLL components required
n Single +3.3V power supply
n Low power: 104mA (typ) transmitter, 119mA (typ)
receiver at 80MHz
n ±100mV receiver input threshold
n Loss of lock detection and reporting pin
n Industrial −40 to +85˚C temperature range
n >2.5kV HBM ESD
n Compact, standard 80-pin PQFP package
Block Diagram
DS92LV16
© 2002 National Semiconductor Corporation DS200143
20014301
www.national.com
1 page  
Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
tDSR1
tDSR2
Deserializer PLL
Lock Time from
PWRDWN (with
SYNCPAT)
Deserializer PLL
Lock time from
SYNCPAT
(Note 7)
35MHz
80 MHz
35MHz
80 MHz
3.7
1.9
1.5
0.9
Ideal Deserializer
tRNMI-R Noise Margin Right
Figure 16
(Note 6)
35 MHz
80 MHz
Ideal Deserializer
tRNMI-L Noise Margin Left
Figure 16
(Note 6)
35 MHz
80 MHz
−630
−230
Max
10
4
5
2
+630
+230
Units
µs
µs
µs
µs
ps
ps
ps
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time
required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change
from not receiving data to receiving synchronization patterns (SYNCPATs).
Note 6: tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement
in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: Sync pattern is a fixed pattern with 8-bit of data high followed by 8-bit of data low.
5 www.national.com
5 Page 
AC Timing Diagrams and Test Circuits (Continued)
20014332
tRNMI-L is the noise margin on the left of the above figure. It is a negative value to indicate early with respect to ideal.
tRNMI-R is the noise margin on the right of the above figure. It is a positive value to indicate late with respect to ideal.
FIGURE 16. Deserializer Noise Margin (tRNMI) and Sampling window
VOD = (DO+)–(DO−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
20014316
FIGURE 17. VOD Diagram
20014323
FIGURE 18. Icc vs Freq
11
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