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부품번호 | AT94S10AL-25BQI 기능 |
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기능 | Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller/ up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM | ||
제조업체 | ATMEL Corporation | ||
로고 | |||
전체 30 페이지수
Features
• Multichip Module Containing Field Programmable System Level Integrated Circuit
(FPSLIC™) and Secure Configuration EEPROM Memory
• 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
Programming (ISP)
• Field Programmable System Level Integrated Circuit (FPSLIC)
– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR® Core and
Extensive Data and Instruction SRAM
• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM™
– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
– High-performance DSP Optimized FPGA Core Cell
– Dynamically Reconfigurable In-System – FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic® Designs
– Very Low Static and Dynamic Power Consumption – Ideal for Portable and
Handheld Applications
• Patented AVR Enhanced RISC Architecture
– 120+ Powerful Instructions – Most Single Clock Cycle Execution
– High-performance Hardware Multiplier for DSP-based Systems
– Approaching 1 MIPS per MHz Performance
– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
– Low-power Idle, Power-save, and Power-down Modes
– 100 µA Standby and Typical 2-3 mA per MHz Active
• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
• JTAG (IEEE Std. 1149.1 Compliant) Interface
– Extensive On-chip Debugging Support
– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
• AVR Fixed Peripherals
– Industry-standard 2-wire Serial Interface
– Two Programmable Serial UARTs
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
• Support for FPGA Custom Peripherals
– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
– FPGA Macro Library of Custom Peripherals
• Up to 16 FPGA Supplied Internal Interrupts to AVR
• Up to Four External Interrupts to AVR
• 8 Global FPGA Clocks
– Two FPGA Clocks Driven from AVR Logic
– FPGA Global Clock Access Available from FPGA Core
• Multiple Oscillator Circuits
– Programmable Watchdog Timer with On-chip Oscillator
– Oscillator to AVR Internal Clock Circuit
– Software-selectable Clock Frequency
– Oscillator to Timer/Counter for Real-time Clock
• VCC: 3.0V - 3.6V
• 5V Tolerant I/O
• 3.3V 33 MHz PCI Compliant FPGA I/O
– 20 mA Sink/Source High-performance I/O Structures
– All FPGA I/O Individually Programmable
• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process
• State-of-the-art Integrated PC-based Software Suite including Co-verification
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
Rev. 2314D–FPSLI–2/04
1
Internal Architecture
For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K
FPSLIC datasheet and the AT17 Series Configuration Memory datasheet, available on
the Atmel web site at http://www.atmel.com. This document only describes the differ-
ences between the AT94S Secure FPSLIC and the AT94K FPSLIC.
FPSLIC and
Configurator
Interface
• Fully In-System Programmable and Re-programmable
• When Security Bit Set:
– Data Verification Disabled
– Data Transfer to FPSLIC not Externally Visible
– Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip
Erase
• When Security Bit Cleared:
– Entire Chip Erase Performed
– In-System Programming Enabled
– Data Verification Enabled
External Data pins allow for In-System Programming of the device and setting of the
EEPROM-based security bit. When the security bit is set (active) this programming con-
nection will only respond to a device erase command. Data cannot be read out of the
external programming/data pins when the security bit is set. The part can be re-pro-
grammed, but only after first being erased.
Programming and
Configuration Timing
Characteristics
Atmel’s Configurator Programming Software (CPS), available from the Atmel web site
(http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3191), creates the pro-
gramming algorithm for the embedded configurator; however, if you are planning to
write your own software or use other means to program the embedded configurator, the
section below includes the algorithm and other details.
The FPSLIC Configurator The FPSLIC Configurator is a serial EEPROM memory which is used to load program-
mable devices. This document describes the features needed to program the
Configurator from within its programming mode (i.e., when SER_EN is driven Low).
Reference schematics are supplied for ISP applications.
Serial Bus Overview
The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided
by the programmer, the second wire (cSDA) is a bi-directional signal and is used to pro-
vide data and control information.
Information is transmitted on the serial bus in messages. Each MESSAGE is preceded
by a Start Condition and ends with a Stop Condition. The message consists of an inte-
ger number of bytes, each byte consisting of 8 bits of data, followed by a ninth
Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted
byte. This is possible because devices may only drive the cSDA line Low. The system
must provide a small pull-up current (1 kΩ equivalent) for the cSDA line.
The MESSAGE FORMAT for read and write instructions consists of the bytes shown in
“Bit Format” on page 5.
While writing, the programmer is responsible for issuing the instruction and data. While
reading, the programmer issues the instruction and acknowledges the data from the
Configurator as necessary.
4 AT94S Secure Family
2314D–FPSLI–2/04
4페이지 Programming Summary:
Write to Whole Device
START
SER_EN ≤ Low
PAGE_COUNT ≤ 0
Send Start Condition
BYTE_COUNT ≤ 0
Send Device Address
($A6)
Yes
Send MSB of
EEPROM Address(1)
Yes
Middle Byte
EEPROM Address
Yes
Send LSB of
EEPROM Address(1)
Send Data Byte(2)
BYTE_COUNT ≤
BYTE_COUNT+1
Yes
Yes
No BYTE_COUNT =
T_BYTE?
ACK?
ACK?
ACK?
ACK?
ACK?
No
No
No
No
No
Send Stop Condition
PAGE_COUNT ≤
PAGE_COUNT+1
Yes
Send Start Condition
PAGE_COUNT =
T_PAGE?
No
Send Device Address
($A7)
Yes
SER_EN ≤ High
Low-power (Standby)
Power-Cycle EEPROM
(Latches 1st Byte for
FPGA Download
Operations)
Yes
ACK?
1st Data Byte
Value Changed Due
to Write?
No
No
END
2314D–FPSLI–2/04
AT94S Secure Family
Notes:
1. The 1-Mbit part requires three EEPROM address
bytes; all three bytes must be individually ACK’d by
the EEPROM.
2. Data byte received/sent LSB to MSB.
EEPROM Address is Defined as:
AT17LV010 0000 000x9 x8x7x6x5 x4x3x2x1 x0000 0000
Note: where Xn ... X0 is (PAGE_COUNT)\b
T_BYTE
AT17LV010
128
T_PAGE
AT17LV010
1024
START CONDITION
cSCK
cSDA
STOP CONDITION
cSCK
cSDA
DATA BIT
cSCK
cSDA
ACK BIT
cSCK
cSDA
ACK
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ AT94S10AL-25BQI.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
AT94S10AL-25BQC | Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller/ up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM | ATMEL Corporation |
AT94S10AL-25BQI | Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller/ up to 36 Kbytes of SRAM and On-chip Program Storage EEPROM | ATMEL Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |