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ATF2500C-15JC 데이터시트 PDF




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ATF2500C-15JC 데이터시트, 핀배열, 회로
.comFeatures
UHigh-performance, High-density, Electrically-erasable Programmable Logic Device
t4Fully Connected Logic Array with 416 Product Terms
e10 ns Maximum Pin-to-pin Delay for 5V Operation
eLow-power Edge-sensing “L” Option with <1 mA Standby Current
h24 Flexible Output Macrocells
S– 48 Flip-flops – Two per Macrocell
ta– 72 Sum Terms
a– All Flip-flops, I/O Pins Feed in Independently
D- or T-type Flip-flops
.DProduct Term or Direct Input Pin Clocking
w ATF2500CRegistered or Combinatorial Internal Feedback
wBackward Compatible with ATV2500B/BQL and ATV2500H/L Software
CPLD FamilyAdvanced Electrically-erasable Technology
w– Reprogrammable
Datasmheet– 100% Tested
44-lead Surface Mount Package
.AcToF2500CBlock Diagram
Sheet4U AAAPTTTreFFFl222im555000in000aCCCrQLQyLDescription
taThe ATF2500C is the highest-density PLD available in a 44-pin package. With its fully
connected logic array and flexible macrocell structure, high gate utilization is easily
aobtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) pro-
grammable logic device (PLD) that utilizes Atmel’s proven electrically-erasable
.Dtechnology.
wPin Configurations
Pin Name
wIN
w mCLK/IN
.coI/O
UI/O 0,2,4...
t4I/O 1,3,5...
eeGND
hVCC
Function
Logic Inputs
Pin Clock and Input
Bi-directional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
Ground
+5V Supply
DIP
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 IN
39 IN
38 IN
37 IN
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
22 IN
21 IN
PLCC/LCC/JLCC
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
7
8
9
10
11
12
13
14
15
16
17
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
www.DataSNote:
For ATF2500CQ and ATF2500CQL
(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required.
Rev. 0777G–12/01
1




ATF2500C-15JC pdf, 반도체, 판매, 대치품
Preload and
Observability of
Registered
Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A VIH level on the odd I/O pins will force the
appropriate register high; a VIL will force it low, independent of the polarity or other configura-
tion bit settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12
registers chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2.
In this mode, the contents of the buried register bank will appear on the associated outputs
when the OE control signals are active.
Programming
Software
Support
All family members of the ATF2500C can be designed with Atmel-Synarioand Atmel-Win-
CUPL. ProChipdesigner support will be available Q102.
Additionally, the ATF2500C may be programmed to perform the ATV2500H/Ls functional sub-
set (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In
this case, the ATF2500C becomes a direct replacement or speed upgrade for the
ATV2500H/L. The ATF2500CQ/CQL are direct replacements for the ATV2500BQ/BQL and
the AT2500H/L, including the lack of extra grounds on P4 and P26.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once
programmed, the outputs will read programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observability.
Input and I/O
Pull-ups
All ATF2500C family members have programmable internal input and I/O pinkeeper circuits.
The default condition, including when using the AT2500CQ/CQL family to replace the
AT2500BQ/BQL or AT2500H/L, is that the pinkeepers are not activated.
When pinkeepers are active, inputs or I/Os not being driven externally will maintain their last
driven state. This ensures that all logic array inputs and device outputs are known states.
Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible
drivers (see input and I/O diagrams below).
4 ATF2500C Family
0777G–12/01

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ATF2500C-15JC 전자부품, 판매, 대치품
Output Logic, Registered(1)
Output Logic, Combinatiorial(1)
ATF2500C Family
S2 = 0
S1 S0
00
10
11
Terms in
D/T1
D/T2
84
12 4(1)
84
Output Configuration
Registered (Q1); Q2 FB
Registered (Q1); Q2 FB
Registered (Q1); D/T2 FB
Output
S3 Configuration
0 Active Low
1 Active High
S6 Q1 CLOCK
0 CK1
1 CK1 • PIN1
S4 Register 1 Type
0D
1T
S7 Q2 CLOCK
0 CK2
1 CK2 • PIN1
S5 Register 2 Type
0D
1T
S5
X
X
X
1
0
Note:
S2 = 1
Terms in
S1 S0 D/T1 D/T2 Output Configuration
0
0
4(1)
4
Combinatorial (8 Terms);
Q2 FB
0
1
4
4
Combinatorial (4 Terms);
Q2 FB
1
0
4(1)
4(1)
Combinatorial (12 Terms);
Q2 FB
1
1
4(1)
4
Combinatorial (8 Terms);
D/T2 FB
1
1
4
4
Combinatorial (4 Terms);
D/T2 FB
1. These four terms are shared with D/T1.
Clock Option
Note: 1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
0777G–12/01
7

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