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PDF ATMEGA603L Data sheet ( Hoja de datos )
| Número de pieza | ATMEGA603L | |
| Descripción | 8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Utilizes the AVR® Enhanced RISC Architecture
• 121 Powerful Instructions - Most Single Clock Cycle Execution
• 128K bytes of In-System Reprogrammable Flash (ATmega103/L)
64K bytes of In-System Reprogrammable Falsh (ATmega603/L)
– Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
• 4K bytes EEPROM (ATmega103/L)
2K bytes of EEPROM (ATmega603/L)
– Endurance: 100,000 Write/Erase Cycles
• 4K bytes Internal SRAM
• 32 x 8 General Purpose Working Registers + Peripheral Control Registers
• 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
• Programmable Serial UART + SPI Serial Interface
• VCC Supply
– 2.7 - 6.0V (ATmega603L/ATmega103L)
– 4.0 - 6.0V (ATmega603/ATmega103)
• Fully Static Operation
– 0 - 6 MHz (ATmega603/ATmega103)
– 0 - 4 MHz (ATmega603L/ATmega103L)
• Up to 6 MIPS Throughput at 6 MHz
• RTC with Separate Oscillator
• Two 8-Bit Timer/Counters with Separate Prescaler and PWM
• One 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and
Dual 8-, 9- or 10-Bit PWM
• Programmable Watchdog Timer with On-Chip Oscillator
• On-Chip Analog Comparator
• 8-Channel, 10-Bit ADC
• Low Power Idle, Power Save and Power Down Modes
• Software Selectable Clock Frequency
• Programming Lock for Software Security
Pin Configuration
TQFP
8-Bit
Microcontroller
with 64K/128K
Bytes In-System
Programmable
Flash
ATmega603
ATmega603L
ATmega103
ATmega103L
Preliminary
ATmega103/L
ATmega103/L
Rev. 0945AS–05/98
1
1 page  
ATmega603/L and ATmega103/L
Figure 4. The ATmega603/103 AVR Enhanced RISC Architecture
AVR ATmega103 Architecture
Data Bus 8-bit
32K/64K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Status
and Test
32 x 8
General
Purpose
Registers
ALU
Peripherals
4K x 8
Data
SRAM
2K/4K x 8
EEPROM
The AVR uses a Harvard architecture concept - with sepa-
rate memories and buses for program and data. The pro-
gram memory is executed with a single level pipelining.
While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system programmable Flash
memory. With a few exceptions, AVR instructions have a
single 16-bit word format, meaning that every program
memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 4000 bytes data SRAM can be easily accessed
through the five different addressing modes supported in
the AVR architecture.
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address, the higher the
priority.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
5
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| PDF Descargar | [ Datasheet ATMEGA603L.PDF ] | |
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