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ATTINY26 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 ATTINY26은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 ATTINY26 자료 제공

부품번호 ATTINY26 기능
기능 8-bit Microcontroller with 2K Bytes Flash
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고


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ATTINY26 데이터시트, 핀배열, 회로
Features
High-performance, Low-power AVR® 8-bit Microcontroller
RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– 8-bit Timer/Counter with Separate Prescaler
– 8-bit High-speed Timer with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Non-overlapping Inverted PWM Output Pins
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
11 Single Ended Channels
8 Differential ADC Channels
7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– On-chip Analog Comparator
– External Interrupt
– Pin Change Interrupt on 11 Pins
– Programmable Watchdog Timer with Separate On-chip Oscillator
Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power-down Modes
– Power-on Reset and Programmable Brown-out Detection
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator
I/O and Packages
– 20-lead PDIP/SOIC: 16 Programmable I/O Lines
– 32-lead QFN/MLF: 16 programmable I/O Lines
Operating Voltages
– 2.7V - 5.5V for ATtiny26L
– 4.5V - 5.5V for ATtiny26
Speed Grades
– 0 - 8 MHz for ATtiny26L
– 0 - 16 MHz for ATtiny26
Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L
– Active 16 MHz, 5V and 25°C: Typ 15 mA
– Active 1 MHz, 3V and 25°C: 0.70 mA
– Idle Mode 1 MHz, 3V and 25°C: 0.18 mA
– Power-down Mode: < 1 µA
8-bit
Microcontroller
with 2K Bytes
Flash
ATtiny26
ATtiny26L
1477K–AVR–08/10




ATTINY26 pdf, 반도체, 판매, 대치품
Block Diagram
Figure 1. The ATtiny26(L) Block Diagram
VCC
GND
PROGRAM
COUNTER
8-BIT DATA BUS
INTERNAL
OSCILLATOR
STACK
POINTER
WATCHDOG
TIMER
AVCC
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
INTERRUPT
UNIT
PROGRAMMING
LOGIC
ISP INTERFACE
EEPROM
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
OSCILLATORS
DATA REGISTER
PORT A
DATA DIR.
REG.PORT A
ADC
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT A DRIVERS
PORT B DRIVERS
PA0-PA7
PB0-PB7
4 ATtiny26(L)
1477K–AVR–08/10

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ATTINY26 전자부품, 판매, 대치품
ATtiny26(L)
AVR CPU Core
Architectural
Overview
The fast-access Register File concept contains 32 x 8-bit general purpose working registers with
a single clock cycle access time. This means that during one single clock cycle, one ALU (Arith-
metic Logic Unit) operation is executed. Two operands are output from the Register File, the
operation is executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as 16-bit pointers for indirect memory access. These pointers
are called the X-, Y-, and Z-pointers, and they can address the Register File and the Flash pro-
gram memory.
Figure 2. The ATtiny26(L) AVR Enhanced RISC Architecture
8-bit Data Bus
1024 x 16
Program
FLASH
Program
Counter
Status
and Test
Control
Registers
Interrupt
Unit
Instruction
Register
Instruction
Decoder
Control Lines
32 x 8
General
Purpose
Registers
ALU
Universal
Serial Interface
ISP Unit
2 x 8-bit
Timer/Counter
Watchdog
Timer
128 x 8
SRAM
ADC
128 byte
EEPROM
Analog
Comparator
I/O Lines
1477K–AVR–08/10
The ALU supports arithmetic and logic functions between registers or between a constant and a
register. Single register operations are also executed in the ALU. Figure 2 shows the
ATtiny26(L) AVR Enhanced RISC microcontroller architecture. In addition to the register opera-
tion, the conventional memory addressing modes can be used on the Register File as well. This
is enabled by the fact that the Register File is assigned the 32 lowermost Data Space addresses
($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, Timer/Counters, A/D Converters, and other I/O functions. The I/O Memory can be
accessed directly, or as the Data Space locations following those of the Register File, $20 - $5F.
The AVR uses a Harvard architecture concept with separate memories and buses for program
and data memories. The program memory is accessed with a two stage pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This
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