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PDF ATTINY26L Data sheet ( Hoja de datos )
| Número de pieza | ATTINY26L | |
| Descripción | 8-bit Microcontroller with 2K Bytes Flash | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• RISC Architecture
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
• Data and Non-volatile Program Memory
– 2K Bytes of In-System Programmable Program Memory Flash
Endurance: 10,000 Write/Erase Cycles
– 128 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– 8-bit Timer/Counter with Separate Prescaler
– 8-bit High-speed Timer with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Non-overlapping Inverted PWM Output Pins
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
11 Single Ended Channels
8 Differential ADC Channels
7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– On-chip Analog Comparator
– External Interrupt
– Pin Change Interrupt on 11 Pins
– Programmable Watchdog Timer with Separate On-chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power-down Modes
– Power-on Reset and Programmable Brown-out Detection
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator
• I/O and Packages
– 20-lead PDIP/SOIC: 16 Programmable I/O Lines
– 32-lead QFN/MLF: 16 programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V for ATtiny26L
– 4.5V - 5.5V for ATtiny26
• Speed Grades
– 0 - 8 MHz for ATtiny26L
– 0 - 16 MHz for ATtiny26
• Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L
– Active 16 MHz, 5V and 25°C: Typ 15 mA
– Active 1 MHz, 3V and 25°C: 0.70 mA
– Idle Mode 1 MHz, 3V and 25°C: 0.18 mA
– Power-down Mode: < 1 µA
8-bit
Microcontroller
with 2K Bytes
Flash
ATtiny26
ATtiny26L
1477K–AVR–08/10
1 page  
ATtiny26(L)
Pin Descriptions
VCC
GND
AVCC
Port A (PA7..PA0)
Port B (PB7..PB0)
XTAL1
XTAL2
Digital supply voltage pin.
Digital ground pin.
AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter. See page 94 for details on operating of the ADC.
Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide internal
pull-ups (selected for each bit). Port A has alternate functions as analog inputs for the ADC and
analog comparator and pin change interrupt as described in “Alternate Port Functions” on page
46.
Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide internal pull-
ups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin PB7 as an I/O
pin, instead of RESET pin, program (“0”) RSTDISBL Fuse. Port B has alternate functions for the
ADC, clocking, timer counters, USI, SPI programming, and pin change interrupt as described in
“Alternate Port Functions” on page 46.
An External Reset is generated by a low level on the PB7/RESET pin. Reset pulses longer than
50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Output from the inverting oscillator amplifier.
1477K–AVR–08/10
5
5 Page 
ATtiny26(L)
Stack Pointer – SP The ATtiny26(L) Stack Pointer is implemented as an 8-bit register in the I/O space location $3D
($5D). As the ATtiny26(L) data memory has 224 ($E0) locations, eight bits are used.
Bit
$3D ($5D)
Read/Write
Initial Value
7
SP7
R/W
0
6
SP6
R/W
0
5
SP5
R/W
0
4
SP4
R/W
0
3
SP3
R/W
0
2
SP2
R/W
0
1
SP1
R/W
0
0
SP0
R/W
0
SP
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when an address is pushed onto the
Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when an address
is popped from the Stack with return from subroutine RET or return from interrupt RETI.
Program and Data
Addressing Modes
The ATtiny26(L) AVR Enhanced RISC microcontroller supports powerful and efficient address-
ing modes for access to the Flash program memory, SRAM, Register File, and I/O Data
memory. This section describes the different addressing modes supported by the AVR architec-
ture. In the figures, OP means the operation code part of the instruction word. To simplify, not all
figures show the exact location of the addressing bits.
Register Direct, Single Figure 5. Direct Single Register Addressing
Register Rd
Register Direct, Two
Registers Rd and Rr
The operand is contained in register d (Rd).
Figure 6. Direct Register Addressing, Two Registers
1477K–AVR–08/10
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ATTINY26L.PDF ] | |
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