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AV16652DL 데이터시트 PDF




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부품번호 AV16652DL 기능
기능 2.5V/3.3V 16-bit bus transceiver/register 3-State
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AV16652DL 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74ALVT16652
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
Product specification
Supersedes data of 1996 Aug 13
IC23 Data Handbook
1998 Feb 13
Philips
Semiconductors




AV16652DL pdf, 반도체, 판매, 대치품
Philips Semiconductors
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
LOGIC DIAGRAM
nOEBA
nOEAB
nCPBA
nSBA
nCPAB
nSAB
1of 8 Channels
nA0
1D
C1
Q
1D
C1
Q
Product specification
74ALVT16652
nB0
nA1 nB1
nA2 nB2
nA3 nB3
nA4 DETAIL A X 7 nB4
nA5 nB5
nA6 nB6
nA7 nB7
SH00065
FUNCTION TABLE
nOEAB
nOEBA
INPUTS
nCPAB nCPBA nSAB nSBA
DATA I/O
nAx nBx
OPERATING MODE
L
L
H
H or L
H or L
X
X
H ↑ ↑ XX
Input
Input
Isolation
Store A and B data
X
H
H
H
H or L
X
X
↑ ↑ ** X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
L
X H or L
L↑↑
X
X
X Unspecified
** output*
Input
Hold A, Store B
Store B in both registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
H
HXX
H H or L X
LX
HX
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus
Stored B data to A bus
H=
L=
X=
=
*
**
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the nOEBA and nOEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (nSAB and nSBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must
be staggered in order to load both registers.
1998 Feb 13
4

4페이지










AV16652DL 전자부품, 판매, 대치품
Philips Semiconductors
2.5V/3.3V 16-bit bus transceiver/register
(3-State)
Product specification
74ALVT16652
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = –40°C to +85°C.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN TYP1 MAX
UNIT
VIK
VOH
VOL
VRST
II
IOFF
IHOLD
IEX
IPU/PD
Input clamp voltage
High-level output voltage
Low–level output voltage
Power-up output low voltage6
Input leakage current
Off current
Bus Hold current
Data inputs7
Current into an output in the
High state when VO > VCC
Power up/down 3-State output
current3
VCC = 3.0V; IIK = –18mA
VCC = 3.0 to 3.6V; IOH = –100µA
VCC = 3.0V; IOH = –32mA
VCC = 3.0V; IOL = 100µA
VCC = 3.0V; IOL = 16mA
VCC = 3.0V; IOL = 32mA
VCC = 3.0V; IOL = 64mA
VCC = 3.6V; IO = 1mA; VI = VCC or GND
VCC = 3.6V; VI = VCC or GND
VCC = 0 or 3.6V; VI = 5.5V
Control pins
VCC = 3.6V; VI = 5.5V
VCC = 3.6V; VI = VCC
I/O Data pins4
VCC = 3.6V; VI = 0
VCC = 0V; VI or VO = 0 to 4.5V
VCC = 3V; VI = 0.8V
VCC = 3V; VI = 2.0V
VCC = 3.0V; VI = 0V to 3.6V
VCC–0.2
2.0
75
–75
±500
–0.85
VCC
2.3
0.07
0.25
0.3
0.4
0.1
0.1
0.1
0.5
0.1
0.1
130
–140
VO = 5.5V; VCC = 3.0V
50
VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC
OE/OE = Don’t care
40
–1.2
0.2
0.4
0.5
0.55
0.55
±1
10
20
10
-5
±100
125
±100
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
ICCH
VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0
0.07 0.14
ICCL
ICCZ
Quiescent supply current
VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0
VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05
3.2 7
0.07 0.14
mA
ICC
Additional supply current per
input pin2
VCC = 3V to 3.6V; One input at VCC–0.6V,
Other inputs at VCC or GND
0.04 0.4 mA
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND
3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a
transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only.
4. Unused pins at VCC or GND.
5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground.
6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 13
7

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