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PDF AV9110-02CN14 Data sheet ( Hoja de datos )
| Número de pieza | AV9110-02CN14 | |
| Descripción | Serially Programmable Frequency Generator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
AV9110
Serially Programmable Frequency Generator
General Description
The AV9110 generates user specified clock frequencies using
an externally generated input reference, such as 14.318 MHz
or 10.00 MHz crystal connected between pins 1 and 14.
Alternately, a TTL input reference clock signal can be used.
The output frequency is determined by a 24-bit digital word
entered through the serial port. The serial port enables the
user to change the output frequency on-the-fly.
The clock outputs utilize CMOS level output buffers that
operate up to 130 MHz.
Features
• Complete user programmability of output frequency
through serial input data port
• On-chip Phase-Locked Loop for clock generation
• Generates accurate frequencies up to 130 MHz
• Tristate CMOS outputs
• 5 volt power supply
• Low power CMOS technology
• 14-pin DIP or 150-mil SOIC
• Very low jitter
• Wide operating range VCO
Block Diagram
Applications
Graphics: The AV9110 generates low jitter, high speed pixel
(or dot) clocks. It can be used to replace multiple expensive
high speed crystal oscillators. The flexibility of this device
allows it to generate nonstandard graphics clocks, allowing
the user to program frequencies on-the-fly.
9110 Rev F 5/30/00
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
1 page  
AV9110
Output Divider Turth Tables
COD1
0
0
1
1
Table 2
COD0
0
1
0
1
CLK/X
Output Divide
(X)
1
2
4
8
COD1
0
0
1
1
Table 3
COD0
0
1
0
1
VCO
Output Divide
(R)
1
2
4
8
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
2 MHz < fREF < 32 MHz
fREF
200 kHz <
< 5MHz
M
50 MHz < f <250 MHz
VCO
fREF = Input reference frequency
M = Reference divide, 3 to 127
f = VCO output frequency
VCO
fVCO < 250 MHz
fCLK = CLK or CLK/X output frequency
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
fVCO =
N•V• fREF
Where
N = VCO divided, 3 to 127
M M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
The 2 output drivers then give the following frequencies:
fCLK =
fVCO = N•V• fREF or fREF (output mixable by bit 17)
R MR
fCLK/X =
fVCO =
R•X
fVCLK
X
Where R, X = output dividers 1, 2, 4 or 8
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
5
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