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PDF AV9170 Data sheet ( Hoja de datos )

Número de pieza AV9170
Descripción Clock Synchronizer and Multiplier
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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Integrated
Circuit
Systems, Inc.
AV9170
Clock Synchronizer and Multiplier
General Description
The AV9170 generates an output clock which is synchronized
to a given continuous input clock with zero delay (±1ns at 5V
VDD). Using ICS’s proprietary phase-locked loop (PLL) ana-
log CMOS technology, the AV9170 is useful for regenerating
clocks in high speed systems where skew is a major concern.
By the use of the two select pins, multiples or divisions of the
input clock can be generated with zero delay (see Tables 2 and
3). The standard versions produce two outputs, where CLK2
is always a divide by two version of CLK1.
The AV9170 is also useful to recover poor duty cycle clocks.
A 50 MHz signal with a 20/80% duty cycle, for example, can
be regenerated to the 48/52% typical of the part.
The AV9170 allows the user to control the PLL feedback,
making it possible, with an additional 74F240 octal buffer (or
other such device that offers controlled skew outputs), to
synchronize up to 8 output clocks with zero delay compared to
the input (see Figure 1). Application notes for the AV9170 are
available. Please consult ICS.
Features
• On-chip Phase-Locked Loop for clocks synchronization
• Synchronizes frequencies up to 107 MHz
(output) @ 5.0V
• ±1ns skew (max) between input & output clocks @ 5.0V
• Can recover poor duty cycle clocks
• CLK1 to CLK2 skew controlled to within ±1ns @ 5.0V
• 3.0 - 5.5V supply range
• Low power CMOS technology
• Small 8-pin DIP or SOIC package
• On chip loop filter
• AV9170-01, -04 for output clocks 20-107 MHz @ 5.0V,
20 - 66.7 MHz @ 3.3V
• AV9170-02, -05 for output clocks 5-26.75 MHz @ 5.0V,
5 - 16.7 MHz @ 3.3V
Block Diagram
AV 9170 Rev E 9/24/99
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.

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AV9170 pdf
AV9170
Using CLK2 Feedback
Connecting CLK2 to FBIN as shown in Figure 6 will cause all
of the rising edges to be aligned (Figure 8).
Using CLK1 Feedback
With CLK1 connected to FBIN as shown in Figure 7, the
input and CLK1 output will be aligned on the rising edge, but
CLK2 can be either rising or falling (Figure 9).
Figure 6:
Figure 7:
For CLK2 frequencies 10 - 53 MHz* (-04)
For CLK2 frequencies 2.5 - 13.37 MHz (-05)
*Maximum 33.3 MHz @ 3.3V (-04), 8.33 MHz @ 3.3V (-05)
For CLK1 frequencies 20 - 107 MHz† (-04)
For CLK1 frequencies 5 - 26.75 MHz (-05)
†Maximum 66.7 MHz @ 3.3V (-04), 16.7 MHz @ 3.3V (-05)
Table 4:
Functionality Table for AV9170-04, -05
with CLK2 Feedback
FS1 FS0
00
01
10
11
CLK1
INx6
INx10
INx12
INx20
CLK2
INx3
INx5
INx6
INx10
Table 5:
Functionality Table for AV9170-04, -05
with CLK1 Feedback
FS1 FS0
00
01
10
11
CLK1
INx3
INx5
INx6
INx10
CLK2
INx1.5
INx2.5
INx3
INx5
Figure 8:
Input and Output Clock Waveforms
with CLK2 Connected to FBIN
Figure 9:
Input and Output Clock Waveforms
with CLK1 Connected to FBIN
5

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AV9170 arduino
AV9170
8-Pin DIP PACKAGE
8-Pin SOIC PACKAGE
Ordering Information
AV9170-xxCN8 (8 Lead Plastic DIP [300 mils] )
AV9170-xxCS8 (8 Lead SOIC [150 mils] )
Example:
ICS XXXX - PPP M X#W
Lead Count & Package Width
Lead Count = 1, 2 or 3 digits
W = 0.3" SOIC or 0.6" DIP; None = Standard Width
Package Type
N = DIP (Plastic)
S = SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device; AV = ICS (West Coast)
For the SOIC package, the AV9170-01 is marked AV70-1 and the AV9170-02 is marked AV70-2.
ICS reserves the right to make changes in the device data identified in this publication
11 without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.

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