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M27V322-150P1 데이터시트 PDF




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부품번호 M27V322-150P1 기능
기능 32 Mbit 2Mb x16 Low Voltage UV EPROM and OTP EPROM
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M27V322-150P1 데이터시트, 핀배열, 회로
M27V322
32 Mbit (2Mb x16) Low Voltage UV EPROM and OTP EPROM
s 3.3V ± 10% SUPPLY VOLTAGE in READ
OPERATION
s READ ACCESS TIME
– 100ns at VCC = 3.0V to 3.6V
s PIN COMPATIBLE WITH M27C322
s WORD-WIDE CONFIGURABLE
s 32 Mbit MASK ROM REPLACEMENT
s LOW POWER CONSUMPTION
– Active Current 30mA at 5MHz
– Stand-by Current 60µA
s PROGRAMMING VOLTAGE: 12V ± 0.25V
s PROGRAMMING TIME: 50µs/word
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code: 0034h
DESCRIPTION
The M27V322 is a 32 Mbit EPROM offered in the
UV range (ultra violet erase) and OTP range. It is
ideally suited for microprocessor systems requir-
ing large data or program storage. It is organised
as 2 MWords of 16 bit. The pin-out is compatible
with a 32 Mbit Mask ROM.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V322 is offered in PDIP42 package.
42
1
FDIP42W (F)
42
1
PDIP42 (P)
Figure 1. Logic Diagram
VCC
21
A0-A20
16
Q0-Q15
E
GVPP
M27V322
VSS
AI03050
March 2000
1/13




M27V322-150P1 pdf, 반도체, 판매, 대치품
M27V322
Table 5. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
High Speed
10ns
0 to 3V
1.5V
Standard
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
High Speed
3V
0V
Standard
2.4V
0.4V
1.5V
2.0V
0.8V
AI01822
Figure 4. AC Testing Load Circuit
1.3V
1N914
DEVICE
UNDER
TEST
3.3k
CL
OUT
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)
Symbol
Parameter
Test Condition
CIN Input Capacitance
VIN = 0V
COUT
Output Capacitance
VOUT = 0V
Note: 1. Sampled only, not 100% tested.
Min Max Unit
10 pF
12 pF
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor is used on every device between VCC
and VSS. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween VCC and VSS for every eight devices. This
capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.
4/13

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M27V322-150P1 전자부품, 판매, 대치품
Table 10. MARGIN MODE AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)
Symbol
Alt
Parameter
Test Condition Min
tA9HVPH
tAS9 VA9 High to VPP High
2
tVPHEL
tVPS VPP High to Chip Enable Low
2
tA10HEH
tAS10 VA10 High to Chip Enable High (Set)
1
tA10LEH
tAS10 VA10 Low to Chip Enable High (Reset)
1
tEXA10X
tAH10 Chip Enable Transition to VA10 Transition
1
tEXVPX
tVPH Chip Enable Transition to VPP Transition
2
tVPXA9X
tAH9 VPP Transition to VA9 Transition
2
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
Table 11. Programming Mode AC Characteristics (1)
(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12V ± 0.25V)
Symbol
Alt
Parameter
Test Condition Min
tAVEL
tAS Address Valid to Chip Enable Low
1
tQVEL
tDS Input Valid to Chip Enable Low
1
tVCHEL
tVCS VCC High to Chip Enable Low
2
tVPHEL
tOES VPP High to Chip Enable Low
1
tVPLVPH
tPRT VPP Rise Time
50
tELEH
tPW Chip Enable Program Pulse Width (Initial)
45
tEHQX
tDH Chip Enable High to Input Transition
2
tEHVPX
tOEH Chip Enable High to VPP Transition
2
tVPLEL
tVR VPP Low to Chip Enable Low
1
tELQV
tDV Chip Enable Low to Output Valid
tEHQZ (2)
tDFP Chip Enable High to Output Hi-Z
0
tEHAX
tAH Chip Enable High to Address Transition
0
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
M27V322
Max Unit
µs
µs
µs
µs
µs
µs
µs
Max Unit
µs
µs
µs
µs
ns
55 µs
µs
µs
µs
1 µs
130 ns
ns
Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27V322 are in the "1"
state. Data is introduced by selectively program-
ming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a "0" to a "1" is by die exposition to ultravi-
olet light (UV EPROM). The M27V322 is in the
programming mode when VPP input is at 12.V,
GVPP is at VIH and E is pulsed to VIL. The data to
be programmed is applied to 16 bits in parallel to
the data output pins. The levels required for the
address and data inputs are TTL. VCC is specified
to be 6.25V ± 0.25V.
7/13

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