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M24C64-BN3TP 데이터시트 PDF




STMicroelectronics에서 제조한 전자 부품 M24C64-BN3TP은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 M24C64-BN3TP 자료 제공

부품번호 M24C64-BN3TP 기능
기능 64Kbit and 32Kbit Serial IC Bus EEPROM
제조업체 STMicroelectronics
로고 STMicroelectronics 로고


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M24C64-BN3TP 데이터시트, 핀배열, 회로
M24C64
M24C32
64Kbit and 32Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
Two-Wire I2C Serial Interface
Supports 400kHz Protocol
Single Supply Voltage:
– 4.5 to 5.5V for M24Cxx
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
Write Control Input
BYTE and PAGE WRITE (up to 32 Bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40-Year Data Retention
Table 1. Product List
Reference
Part Number
M24C64
M24C64
M24C64-W
M24C64-R
M24C32
M24C32
M24C32-W
M24C32-R
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
2x3mm² (MLP)
January 2005
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M24C64-BN3TP pdf, 반도체, 판매, 대치품
M24C64, M24C32
SUMMARY DESCRIPTION
These I2C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 8192 x 8 bits (M24C64) and 4096 x 8 bits
(M24C32).
Figure 2. Logic Diagram
VCC
3
E0-E2
SCL
WC
M24C64
M24C32
SDA
VSS
AI01844B
I2C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I2C bus definition.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in Table 3.), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 2. Signal Names
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL Serial Clock
WC Write Control
VCC
Supply Voltage
VSS
Ground
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. At Power-up, the
internal reset is held active until VCC has reached
the Power On Reset (POR) threshold voltage, and
all operations are disabled – the device will not re-
spond to any command. In the same way, when
VCC drops from the operating voltage, below the
Power On Reset (POR) threshold voltage, all op-
erations are disabled and the device will not re-
spond to any command.
A stable and valid VCC (as defined in Table 9. and
Table 10.) must be applied before applying any
logic signal.
Figure 3. DIP, SO, TSSOP and UFDFPN
Connections
M24C64
M24C32
E0 1
E1 2
8 VCC
7 WC
E2 3
6 SCL
VSS 4
5 SDA
AI01845C
Note: See PACKAGE MECHANICAL section for package dimen-
sions, and how to identify pin-1.
4/26

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M24C64-BN3TP 전자부품, 판매, 대치품
MEMORY ORGANIZATION
The memory is organized as shown in Figure 6..
Figure 6. Block Diagram
WC
E0
E1
E2
SCL
SDA
Control Logic
I/O Shift Register
High Voltage
Generator
Address Register
and Counter
Data
Register
M24C64, M24C32
1 Page
X Decoder
AI06899
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