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부품번호 | FQD3P50 기능 |
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기능 | 500V P-Channel MOSFET | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 9 페이지수
FQD3P50 / FQU3P50
500V P-Channel MOSFET
January 2009
QFET®
General Description
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for electronic lamp ballast based on complimentary
half bridge.
D
GS
D-PAK
FQD Series
GDS
Features
• -2.1A, -500V, RDS(on) = 4.9Ω @VGS = -10 V
• Low gate charge ( typical 18 nC)
• Low Crss ( typical 9.5 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant
I-PAK
FQU Series
G!
S
!
●
●
▶▲
●
!
D
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
EAS
IAR
EAR
dv/dt
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TC = 25°C)
- Continuous (TC = 100°C)
Drain Current - Pulsed
(Note 1)
Gate-Source Voltage
Single Pulsed Avalanche Energy
(Note 2)
Avalanche Current
(Note 1)
Repetitive Avalanche Energy
(Note 1)
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C) *
Power Dissipation (TC = 25°C)
- Derate above 25°C
(Note 3)
Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds
Thermal Characteristics
Symbol
RθJC
RθJA
RθJA
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient *
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
©2009 Fairchild Semiconductor Internati
FQD3P50 / FQU3P50
-500
-2.1
-1.33
-8.4
± 30
250
-2.1
5.0
-4.5
2.5
50
0.4
-55 to +150
300
Typ Max
-- 2.5
-- 50
-- 110
Units
V
A
A
A
V
mJ
A
mJ
V/ns
W
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
Rev. A2, January 2009
Typical Characteristics (Continued)
1.2
1.1
1.0
0.9
0.8
-100
※ Notes :
1. VGS = 0 V
2. ID = -250 μA
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 7. Breakdown Voltage Variation
vs. Temperature
Operation in This Area
is Limited by R DS(on)
101
100 µs
1 ms
100 10 ms
DC
10-1
10-2
100
※ Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
101 102
-VDS, Drain-Source Voltage [V]
103
Figure 9. Maximum Safe Operating Area
2.5
2.0
1.5
1.0
0.5
0.0
-100
※ Notes :
1. VGS = -10 V
2. ID = -1.35 A
-50 0 50 100 150
TJ, Junction Temperature [oC]
200
Figure 8. On-Resistance Variation
vs. Temperature
2.5
2.0
1.5
1.0
0.5
0.0
25
50 75 100 125
TC, Case Temperature [℃]
150
Figure 10. Maximum Drain Current
vs. Case Temperature
100
1 0 -1
D =0.5
0 .2
0 .1
0 .05
0 .02
0 .01
s in g le p u ls e
※ N ote s :
1 . Z θ JC(t) = 2 .5 ℃ /W M a x.
2. D u ty F actor, D =t1/t2
3 . T JM - T C = P D M * Z θ JC(t)
PDM
t1
t2
1 0 -2
1 0 -5
1 0 -4
1 0 -3
1 0 -2
1 0 -1
100
t1, S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
101
©2009 Fairchild Semiconductor International
Rev. A2, January 2009
4페이지 Mechanical Dimensions
TO-252 (DPAK) (FS PKG Code 36)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
millimeters
Part Weight per unit (gram): 0.33
©2009 Fairchild Semiconductor International
Rev. A2, January 2009
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부품번호 | 상세설명 및 기능 | 제조사 |
FQD3P50 | 500V P-Channel MOSFET | Fairchild Semiconductor |
FQD3P50TM_F085 | 500V P-Channel MOSFET | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |