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부품번호 FQD45N03L 기능
기능 N-Channel Logic Level PWM Optimized Power MOSFET
제조업체 Fairchild Semiconductor
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FQD45N03L 데이터시트, 핀배열, 회로
March 2004
FQD45N03L
N-Channel Logic Level PWM Optimized Power MOSFET
General Description
This device employs a new advanced MOSFET technology
and features low gate charge while maintaining low on-
resistance.
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
Applications
• DC/DC converters
Features
• Fast switching
• rDS(ON) = 0.018(Typ), VGS = 10V
• rDS(ON) = 0.028(Typ), VGS = 5V
• Qg (Typ) = 9nC, VGS = 5V
• Qgd (Typ) =3nC
• CISS (Typ) =970pF
DRAIN (FLANGE)
D
GATE
SOURCE
TO-252
G
S
MOSFET Maximum Ratings TC=25°C unless otherwise noted
Symbol
VDSS
VGS
ID
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 4.5V)
Continuous (TC = 25oC, VGS = 10V, RθJA=52oC)
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Ratings
30
±20
20
20
8
Figure 4
41
0.33
-55 to 150
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance Junction to Case TO-252
Thermal Resistance Junction to Ambient TO-252
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
3
100
52
Package Marking and Ordering Information
Device Marking
FQD45N03L
Device
FQD45N03L
Package
TO-252AA
Reel Size
330mm
Tape Width
16mm
Units
V
V
A
A
A
A
W
W/oC
oC
oC/W
oC/W
oC/W
Quantity
2500 units
©2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1




FQD45N03L pdf, 반도체, 판매, 대치품
Typical Characteristic (Continued) TC = 25°C unless otherwise noted
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
40 VDD = 15V
30
TJ = 150oC
20
10
0
1
TJ = 25oC
TJ = -55oC
234
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
5
50
VGS = 10V
40
30
VGS = 5V
VGS = 4V
20
10
0
0
VGS = 3V
TC =
25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.5 1.0 1.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.0
Figure 6. Saturation Characteristics
40
ID = 10A
ID = 20A
30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
20 1.0
10
2
468
VGS, GATE TO SOURCE VOLTAGE (V)
10
Figure 7. Drain To Source On Resistance vs Gate
Voltage And Drain Current
1.2
VGS = VDS, ID = 250µA
1.0
0.8
0.6
0.5
-80
VGS = 10V, ID =20A
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
Figure 8. Normalized Drain To Source On
Resistance vs Junction Temperatrue
1.2
ID = 250µA
1.1
1.0
0.4
-80
-40 0
40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
0.9
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
Figure 10. Normalized Drain To Source
Breakdown Voltage vs Junction Temperature
©2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1

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FQD45N03L 전자부품, 판매, 대치품
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the applications ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
125
100
75
PDM
=
-(--T----J---M------–-----T---A-----)
ZθJA
(EQ. 1)
50
RθJA = 33.32 + 23.84/(0.268+Area)
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the parts current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designers preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
RθJA
=
33.32 +
------------2---3---.--8---4-------------
(0.268 + Area)
(EQ. 2)
25
0.01
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
©2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1

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부품번호상세설명 및 기능제조사
FQD45N03L

N-Channel Logic Level PWM Optimized Power MOSFET

Fairchild Semiconductor
Fairchild Semiconductor

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