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부품번호 | FQS4900 기능 |
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기능 | Dual N & P-Channel/ Logic Level MOSFET | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 9 페이지수
FQS4900
Dual N & P-Channel, Logic Level MOSFET
August 2000
QFETTM
General Description
These dual N and P-channel enhancement mode power
field effect transistors are produced using Fairchild’s
proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. This device is well
suited for high interface in telephone sets.
Features
• N-Channel 1.3A, 60V, RDS(on) = 0.55 Ω @ VGS = 10 V
RDS(on) = 0.65 Ω @ VGS = 5 V
P-Channel -0.3A, -300V, RDS(on) = 15.5 Ω @ VGS = -10 V
RDS(on) = 16 Ω @ VGS =- 5 V
• Low gate charge ( typical N-Channel 1.6 nC)
( typical P-Channel 3.6 nC)
• Fast switching
• Improved dv/dt capability
D2
D2
D1
D1
G2
S2
G1
S1
5!
!
"!
!
!
6
7!
!
$#
!
!
8
4
3
2
1
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
ID
IDM
VGSS
dv/dt
PD
TJ, TSTG
Parameter
Drain-Source Voltage
Drain Current
- Continuous (TA = 25°C)
- Continuous (TA = 70°C)
Drain Curent - Pulsed
Gate-Source Voltage
Peak Diode Recovery dv/dt
Power Dissipation (TA = 25°C)
(TA = 70°C)
Operating and Storage Temperature Range
(Note 1)
(Note 2)
N-Channel
P-Channel
60 -300
1.3 -0.3
0.82 -0.19
5.2 -1.2
± 20
7.0 4.5
2.0
1.3
-55 to +150
Thermal Characteristics
Symbol
RθJA
Parameter
Thermal Resistance, Junction-to-Ambient
Typ Max
-- 62.5
Units
V
A
A
A
V
V/ns
W
W
°C
Units
°C/W
©2000 Fairchild Semiconductor International
Rev. A, August 2000
Typical Characteristics : N-Channel (Continued)
1.2
1.1
1.0
0.9
0.8
-100
※ Notes :
1. VGS = 0 V
2. ID = 250 μ A
-50 0 50 100 150
T , Junction Temperature [oC]
J
200
Figure 7. Breakdown Voltage Variation
vs. Temperature
101
100
10-1
10-2
10-1
Operation in This Area
is Limited by R
DS(on)
1 ms
10 ms
100 ms
1s
10 s
DC
※ Notes :
1. T = 25 oC
C
2. T = 150 oC
J
3. Single Pulse
100 101
V , Drain-Source Voltage [V]
DS
102
Figure 9. Maximum Safe Operating Area
2.5
2.0
1.5
1.0
0.5
0.0
-100
※ Notes :
1. VGS = 10 V
2. ID = 0.65 A
-50 0 50 100 150
T , Junction Temperature [oC]
J
200
Figure 8. On-Resistance Variation
vs. Temperature
1.5
1.2
0.9
0.6
0.3
0.0
25
50 75 100 125
TC, Case Temperature [℃]
150
Figure 10. Maximum Drain Current
vs. Case Temperature
D =0.5
101 0.2
0 .1
0 .0 5
0 .0 2
100
0 .0 1
1 0 -1
1 0-4
※ N ote s :
1 . Z θ JC(t) = 6 2 .5 ℃ /W M a x .
2 . D u ty F a c to r, D = t1/t2
3 . T JM - T C = P D M * Z θ JC(t)
s in g le pu ls e
PDM
t1
t2
1 0 -3
1 0 -2
1 0-1
100
101
t1, S q u a re W a v e P u ls e D u ra tio n [s e c ]
102
Figure 11. Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev. A, August 2000
4페이지 Gate Charge Test Circuit & Waveform
Same Type
50KΩ
as DUT
12V 200nF
300nF
VGS
5V
Qg
VGS
VDS
Qgs Qgd
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS
VGS
RG
RL
VDD
VDS
90%
5V
DUT
VGS 10%
td(on)
tr
t on
td(off)
tf
t off
©2000 Fairchild Semiconductor International
Rev. A, August 2000
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
FQS4900 | Dual N & P-Channel/ Logic Level MOSFET | Fairchild Semiconductor |
FQS4901 | 400V Dual N-Channel MOSFET | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |