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E28F002BVT60 데이터시트 PDF




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기능 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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E28F002BVT60 데이터시트, 핀배열, 회로
E
SEE NEW DESIGN RECOMMENDATIONS
REFERENCE ONLY
2-MBIT SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B
n Intel SmartVoltage Technology
5 V or 12 V Program/Erase
3.3 V or 5 V Read Operation
n Very High-Performance Read
5 V: 60 ns Access Time
3 V: 110 ns Access Time
n Low Power Consumption
Max 60 mA Read Current at 5 V
Max 30 mA Read Current at
3.3 V–3.6 V
n x8/x16-Selectable Input/Output Bus
28F200 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F002B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
n Extended Temperature Operation
–40 °C to +85 °C
n Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-, 48-, 56-Lead TSOP
44-Lead PSOP
n Footprint Upgradeable to 4-Mbit and
8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
New Design Recommendations:
For new 2.7 V–3.6 V VCC designs with this device, Intel recommends using the Smart 3 Advanced Boot
Block. Reference Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family datasheet,
order number 290580.
For new 5 V VCC designs with this device, Intel recommends using the 2-Mbit Smart 5 Boot Block. Reference
Smart 5 Flash Memory Family 2, 4, 8 Mbit datasheet, order number 290599.
These documents are also available at Intel’s website, http://www.intel.com/design/flcomp.
December 1997
Order Number: 290531-005




E28F002BVT60 pdf, 반도체, 판매, 대치품
2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Number
-001
-002
-003
-004
-005
REVISION HISTORY
Description
Initial release of datasheet.
Status changed from Product Preview to Preliminary
28F200CV/CE/BE references and information added throughout.
2.7 V CE/BE specs added throughout.
The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,
3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to “Applying VCC Voltages.” These sections completely
changed to clarify VCC ramp requirements.
IPPD 3.3 V Commercial spec changed from 10 to 5 µA.
Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component
values in table. (Component values also rounded off).
tELFL, tELFH, tAVFL changed from 7 to 5 ns for 3.3 V BV-60 commercial and 3.3 V
TBV-80 extended, 10 to 5 ns for 3.3 V BV-80 and BV-120 commercial.
tWHAX and tEHAX changed from 10 to 0 ns.
tPHWL changed from 1000 ns to 800 ns for 3.3 V BV-80, BV-120 commercial.
tPHEL changed from 1000 ns to 800 ns for 3.3 V BV-60, BV-80, and BV-120 commercial.
Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity.
Minor cosmetic changes/edits.
Corrections: “This pin not available on 44-PSOP” inaccurate statement removed from pin
description for WP# pin; Spec “tQWL” corrected to “tQVVL;” intelligent identifier values
corrected; Intel386™ EX block diagram updated because new 386 specs require less
glue logic.
Max program times for parameter and 96-KB main block added.
Specs tELFL and tELFH changed from 5 ns (max) to 0 ns (min).
Specs tEHQZ and tHQZ improved.
New specs tPLPH and tPLQZ added from Specification Update document (297612).
Corrections: Figure 4, corrected pin designation 3 to “NC” from A17 on PA28F200.
Corrected typographical errors in Ordering Information.
Added New Design Recommendations section to cover page.
Updated Erase Suspend/Resume Flowchart
4 SEE NEW DESIGN RECOMMENDATIONS

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E28F002BVT60 전자부품, 판매, 대치품
E
2-MBIT SmartVoltage BOOT BLOCK FAMILY
The 2-Mbit boot block flash memory family provides
full-function, blocked flash memories suitable for a
wide range of applications. These applications
include extended PC BIOS and ROM-able
applications storage, digital cellular phone program
and data storage, telecommunication boot/firmware,
printer firmware/font storage and various other
embedded applications where program and data
storage are required.
Reprogrammable systems, such as personal
computers, are ideal applications for the 2-Mbit
flash memory products. Increasing software
sophistication greatens the probability that a code
update will be required after the PC is shipped. For
example, the emerging of “plug and play” standard
in desktop and portable PCs enables auto-
configuration of ISA and PCI add-in cards.
However, since the plug and play specification
continues to evolve, a flash BIOS provides a cost-
effective capability to update existing PCs. In
addition, the parameter blocks are ideal for storing
the required auto-configuration parameters,
allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single
component, reducing parts costs while increasing
functionality.
The 2-Mbit flash memory products are also
excellent design solutions for digital cellular phone
and telecommunication switching applications
requiring very low power consumption, high-
performance, high-density storage capability,
modular software designs, and a small form factor
package. The 2-Mbit’s blocking scheme allows for
easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four
main blocks of program code and two parameter
blocks of 8 Kbytes each for frequently updated data
storage and diagnostic messages (e.g., phone
numbers, authorization codes).
Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a single flash device. The
boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in place, decreasing RAM
requirements.
1.4 Pinouts
Intel’s SmartVoltage Boot Block architecture
provides upgrade paths in every package pinout to
the 4 or 8-Mbit density. The 28F002B 40-lead
TSOP pinout for space-constrained designs is
shown in Figure 3. The 28F200 44-lead PSOP
pinout follows the industry-standard ROM/EPROM
pinout, as shown in Figure 4. For designs that
require x16 operation but have space concerns,
refer to the 48-lead pinout in Figure 5. Furthermore,
the 28F200 56-lead TSOP pinout shown in Figure 6
provides compatibility with BX/BL family product
packages.
Pinouts for the corresponding 4-Mbit and 8-Mbit
components are also provided for convenient
reference. 2-Mbit pinouts are given on the chip
illustration in the center, with 4-Mbit and 8-Mbit
pinouts going outward from the center.
SEE NEW DESIGN RECOMMENDATIONS
7

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E28F002BVT60

2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel Corporation
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