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E28F004BX-B80 데이터시트 PDF




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기능 4-MBIT (256K X 16/ 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY
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E28F004BX-B80 데이터시트, 핀배열, 회로
4-MBIT (256K X 16 512K X 8)
BOOT BLOCK
FLASH MEMORY FAMILY
28F400BX-T B 28F004BX-T B
Y x8 x16 Input Output Architecture
28F400BX-T 28F400BX-B
For High Performance and High
Integration 16-bit and 32-bit CPUs
Y x8-only Input Output Architecture
28F004BX-T 28F004BX-B
For Space Constrained 8-bit
Applications
Y Upgradeable to Intel’s Smart Voltage
Products
Y Optimized High-Density Blocked
Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
Y Extended Cycling Capability
100 000 Block Erase Cycles
Y Automated Word Byte Write and Block
Erase
Command User Interface
Status Registers
Erase Suspend Capability
Y SRAM-Compatible Write Interface
Y Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
Y Very High-Performance Read
60 80 120 ns Maximum Access Time
30 40 40 ns Maximum Output Enable
Time
Y Low Power Consumption
20 mA Typical Active Read Current
Y Reset Deep Power-Down Input
0 2 mA ICC Typical
Acts as Reset for Boot Operations
Y Extended Temperature Operation
b40 C to a85 C
Y Write Protection for Boot Block
Y Hardware Data Protection Feature
Erase Write Lockout During Power
Transitions
Y Industry Standard Surface Mount
Packaging
28F400BX JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
28F004BX 40-Lead TSOP
Y 12V Word Byte Write and Block Erase
VPP e 12V g5% Standard
VPP e 12V g10% Option
Y ETOXTM III Flash Technology
5V Read
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290451-005




E28F004BX-B80 pdf, 반도체, 판매, 대치품
28F400BX-T B 28F004BX-T B
Program and Erase Automation allows program
and erase operations to be executed using a two-
write command sequence to the CUI The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations including verifications there-
by unburdening the microprocessor or microcontrol-
ler Writing of memory data is performed in word or
byte increments for the 28F400BX family and in byte
increments for the 28F004BX family typically within
9 ms which is a 100% improvement over current
flash memory products
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation
Maximum Access Time of 60 ns (tACC) is achieved
over the commercial temperature range (0 C to
70 C) 5% VCC supply voltage range (4 75V to
5 25V) and 30 pF output load Maximum Access
Time of 70 ns (tACC) is achieved over the commer-
cial temperature range 10% VCC supply range (4 5V
to 5 5V) and 100 pF output load
IPP maximum Program current is 40 mA for x16
operation and 30 mA for x8 operation IPP Erase
current is 30 mA maximum VPP erase and pro-
gramming voltage is 11 4V to 12 6V (VPP e 12V
g 5%) under all operating conditions As an op-
tion VPP can also vary between 10 8V to 13 2V (VPP
e 12V g 10%) with a guaranteed number of 100
block erase cycles
Typical ICC Active Current of 25 mA is achieved
for the X16 products (28F400BX) Typical ICC Ac-
tive Current of 20 mA is achieved for the X8 prod-
ucts (28F400BX 28F004BX) Refer to the ICC active
current derating curves in this datasheet
The 4-Mbit boot block flash memory family is also
designed with an Automatic Power Savings (APS)
feature to minimize system battery current drain and
allows for very low power designs Once the device
is accessed to read array data APS mode will imme-
diately put the memory in static mode of operation
where ICC active current is typically 1 mA until the
next read is initiated
When the CE and RP pins are at VCC and the
BYTE pin (28F400BX-only) is at either VCC or
GND the CMOS Standby mode is enabled where
ICC is typically 50 mA
A Deep Power-Down Mode is enabled when the
RP pin is at ground minimizing power consumption
and providing write protection during power-up con-
ditions ICC current during deep power-down mode
is 0 20 mA typical An initial maximum access time
or Reset Time of 300 ns is required from RP
switching until outputs are valid Equivalently the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recog-
nized When RP is at ground the WSM is reset the
Status Register is cleared and the entire device is
protected from being written to This feature pre-
vents data corruption and protects the code stored
in the device during system reset The system Reset
pin can be tied to RP to reset the memory to nor-
mal read mode upon activation of the Reset pin
With on-chip program erase automation in the
4-Mbit family and the RP functionality for data pro-
tection when the CPU is reset and even if a program
or erase command is issued the device will not rec-
ognize any operation until RP returns to its normal
state
For the 28F400BX Byte-wide or Word-wide In-
put Output Control is possible by controlling the
BYTE pin When the BYTE pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ 0 7 During the byte-
wide mode DQ 8 14 are tri-stated and DQ15 A-1
becomes the lowest order address pin When the
BYTE pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ 0 15
4

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E28F004BX-B80 전자부품, 판매, 대치품
28F400BX-T B 28F004BX-T B
1 4 Pinouts
The 28F400BX 44-Lead PSOP pinout follows the in-
dustry standard ROM EPROM pinout as shown in
Figure 3 Furthermore the 28F400BX 56-Lead
TSOP pinout shown in Figure 4 provides density up-
grades to future higher density boot block memories
The 28F004BX 40-Lead TSOP pinout shown in Fig-
ure 5 is 100% compatible and provides a density
upgrade for the 2-Mbit Boot Block flash memory or
the 28F002BX
Figure 3 PSOP Lead Configuration for x8 x16 28F400BX
290451 – 25
7

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4-MBIT (256K X 16/ 512K X 8) BOOT BLOCK FLASH MEMORY FAMILY

Intel Corporation
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